[moved] Verilog A error for 4 bit serial in parallel out shift register

`include "constants.vams"
`include "disciplines.vams"


module SIPO_4(din, clk, reset, dout0,dout1,dout2,dout3);

output dout0,dout1,dout2,dout3 ;

input din ;
integer din ;
input clk ;
electrical clk ;
input reset ;
electrical reset ;
parameter real vtrans = 0.5;

integer temp[3:0];

analog begin
@ ( cross ( V(clk) - vtrans, +1)) begin
 if (V(reset) == 1) begin
  temp[3] <= 0;
  temp[2] <= 0;
  temp[1] <= 0;
  temp[0] <= 0;
end
 else begin
  temp[3] <= din;
  temp[2] <= temp[3];
  temp[1] <= temp[2];
  temp[0] <= temp[1];
 end
 
dout3 <= temp[3];
dout2 <= temp[2];
dout1 <= temp[1];
dout0 <= temp[0];

endmodule

Error found by spectre during AHDL compile.
    ERROR (VACOMP-1552): "dout3 <= temp[3];<<--? "
        "/tmp_net/libraries/abcd/SIPO_4/veriloga/veriloga.va", line 38:
        Encountered left operand of type node for operator `<='. Specify a real
        or an integer type operand instead.
    ERROR (VACOMP-1552): "dout2 <= temp[2];<<--? "
        "/tmp_net/libraries/abcd/SIPO_4/veriloga/veriloga.va", line 39:
        Encountered left operand of type node for operator `<='. Specify a real
        or an integer type operand instead.
    ERROR (VACOMP-1552): "dout1 <= temp[1];<<--? "
        "/tmp_net/libraries/abcd/SIPO_4/veriloga/veriloga.va", line 40:
        Encountered left operand of type node for operator `<='. Specify a real
        or an integer type operand instead.
    ERROR (VACOMP-1552): "dout0 <= temp[0];<<--? "
        "/tmp_net/libraries/abcd/SIPO_4/veriloga/veriloga.va", line 41:
        Encountered left operand of type node for operator `<='. Specify a real
        or an integer type operand instead.