[SOLVED] [Moved]vcs vlogan help

[bravetanveer]

We have mixed language design, hence we use vlogan but I get the same errors with the below command:

vlogan +v2k -sverilog +libext+.v+.mdl -f list.f +incdir+/rtl/include -timescale=1ns/10ps

Error-[ILWOR] Incorrect Logical Worklib or Reflib
The incorrect logical lib is "work".
Please check your Synopsys setup file.

In the replies, there is no mention of solution to the problem. Can anyone kindly point to the solution ?
Or if anybody can explain the meaning of the error , it would be great help ?

Referring to previous thread https://www.edaboard.com/threads/116343/

Using vlogan is so c alled UUM flow within Synopsys tools. It is needed/recommended only if you have mixed language designs. For pure Verilog/SystemVerilog simply do:

vcs -sverilog -f flist -debug_all
./simv -gui

HTH
Ajeetha, CVC

 

[bravetanveer]

Solution found for this problem is, file 'synopsys_sim.setup' should be present in the directory where vlogan command is getting executed. Sample file is present in examples directory.

Contents are:

WORK > DEFAULT
DEFAULT : ./WORK
--DWARE : ./DWARE

TIMEBASE = NS
CS_ASSERT_STOP_NEXT_WAIT = TRUE

Thanks

We have mixed language design, hence we use vlogan but I get the same errors with the below command:

vlogan +v2k -sverilog +libext+.v+.mdl -f list.f +incdir+/rtl/include -timescale=1ns/10ps

Error-[ILWOR] Incorrect Logical Worklib or Reflib
The incorrect logical lib is "work".
Please check your Synopsys setup file.

In the replies, there is no mention of solution to the problem. Can anyone kindly point to the solution ?
Or if anybody can explain the meaning of the error , it would be great help ?

Referring to previous thread https://www.edaboard.com/threads/116343/