[Moved] problem with connecting to IO Pad in cadence

[z.sh]

Hi, experts
I'm faced with a problem in connecting I/O ESD pad to nmos transistor.
DRC error window shows this error:

Any N+active or N+active cluster connected to an IO pad must be surrounded by a p+ guard ring...

i don't know how to solve it an will be glad if any one can help me.
thanks alot.

 

[Dominik Przyborowski]

Make p+ guard ring around nmosfet which You want to connect to pad.

 

[z.sh]

thanks a lot, but i can't find p+ guard ring in my library, would you tell me what exactly its name is?

 

[Dominik Przyborowski]

You didn't post which process You are using, so I'm not able to post any details.
In some PDKs are predefining guard rings as multipart paths, in others it is possible to make guard ring by placing appropriate contacts or by draw paths of nwell, p+ and "active" layer.

//edit: the contacts to well/substrate are not a cells from any library. Sometimes contacts to substrate exists in main process library but usually are used only on schematic.

 

[z.sh]

You didn't post which process You are using, so I'm not able to post any details.
In some PDKs are predefining guard rings as multipart paths, in others it is possible to make guard ring by placing appropriate contacts or by draw paths of nwell, p+ and "active" layer.

//edit: the contacts to well/substrate are not a cells from any library. Sometimes contacts to substrate exists in main process library but usually are used only on schematic.

Thanks alot for your useful advice I'm designing with TSMC 0.18u technology. I will be thankful if you have more detailsl to add...