[Moved]: possible issues when designing a chip with large burst current

[zhangljz]

Hello, everyone,


I am designing a chip that all the blocks will run simultaneously for about 10ns. So the overall transient current during that period will be very high, about 2A.

Which kind of problems I may have and how to solve?? IR drop ? ringing? ESD?

Thanks

 

[erikl]

IR drop surely could create a problem. Spend wide and multi-layer power supply rails and sufficiently large connections to the power stages.

Ringing could be generated due to the high skew rate and the connection inductances, especially from the bond wires. Estimate their inductances (reduce these by double/multiple parallel wires, perhaps to multiple parallel pads) and include these into your simulation testbench. For postlayout simulation, use LRC extraction.

ESD sensitivity shouldn't be a special problem of your circuit.

Important: In the application, use an external ceramic cap in parallel to and as close as possible to the IC power supply pins, ≈ 1µF.

 

[dick_freebird]

A 2A/10nS surge current will be outside your power supply
loop's ability to track. You must consider your source as
inductive and its setpoint current, the pre-wakeup power
supply draw.

If you are (say) operating at 2.5V and your timing model
only covers 2.35-2.65V, then just to ensure design timing
integrity your core droop (I*Rdistributed) plus supply droop
can account for no more than 0.15V of sag. Let's say you
apportion 100mV to supply and 50mV to internal (and then
you must make it so - 25mOhms=50mV/2A, at a rough 0.03
ohms per square your bussing has already to be oversquare,
W>L, and this leaves nothing for ground bus rise). If you
have thick metal available, use it, with as many power and
ground pads as you can put around the periphery (or bump
right into the core, better still).

That 100mV at the pins has to be made up by close-in
decoupling. Here you also have two things at play, the
net ESR of the cap-bank and the delta-Q for 2A*10nS=20nJ.
dQ=C*dV, so C=20E-9/0.1 = 200nF minimum leaving nothing
for ESR*I. So 1uF ought to do and reduce your dQ droop to
20mV. The other 80mV, can be allocated to ESR*2A, or
ESR<40mOhms (and this should include ESL as the bandwidth
exceeds 1GHz probably, 100MHz fundamental but you need
it to not drop out grossly on the (~1nS?) leading edge risetime.

That's the flavor of it. The details are yours.