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[Moved]: Phase locked loop jitter at 1GHz

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hanikapa

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Hello,
there are many papers about high frequency PLL>10GHZ in the technology below 90nm with LC VCO that their rms jitter is in the range of less than 500fs. I need to know the rms jitter at 1GHZ frequency to compare my design requirements. I could not find good references for them but I gussed that for lower frequencies the state of the art is more than 1ps. can you please introduce me some references? or explain if you have any idea?
 

Re: Phase locked loop jitter at 1GHz

If you can convert phase noise @ offset to jitter RMS,
then there are many commercial PLLs (older vintage)
aimed at the cell phone space which ought to give you
good numbers for their reference designs. Presumably
at 1GHz you would use a >1GHz capable part (rated
frequency is often where the prescaler flakes out, plus
margin, not where you'd find the "sweet spot").

I'd recommend looking at Hittite, RFMD, Peregrine and
so on.

If you have a sine wave oscillator and a fixed noise
amplitude imposed on it, your jitter -will- follow 1/Fin
(because the prescaler input linear region divided by
dV/dt at prescaler input transforms voltage noise to
time noise).

But at 1GHz you might be able to (say) apply a square
(or square-ish) waveform from a LVDS or LVPECL source
and get a much better PN than from a sine output VCO.
If not, go for as much VCO amplitude as possible so as
to maximize dV/dt across threshold.
 

Re: Phase locked loop jitter at 1GHz

I wrote a matlab code to calculate jitter based on phase noise. At 4GHz, the phase noise at 1MHz is -115dBc/Hz and the jitter around 800fs. When I assume a divider by four at the output and I see the phase noise at 1MHz, it is -127dBc/Hz but the phase noise is about 3ps. It is this part that I don't understand if this result is accurate or not, for 1GHz the jitter value is higher than 4GHZ in this code?
 

Re: Phase locked loop jitter at 1GHz

Prescaler should not add much jitter -if- it is presented
a squared up edge to work from. Of course it will add
-some-, but should not be simply 4X.

The formula probably does not speak to this, converting
radians to seconds is simple math only. If you intend a
prescaler then you ought to be doing math like front
end phase noise to jitter, and prescaler "contributed
jitter" (which will depend on input buffer dV/dt, or input
dV/dt if unbuffered) kind of like a noise lineup analysis
but in the time domain. There should be info out there
on how to figure net jitter from a lineup of contributors
(people doing high speed serial links and clock recovery
live with that kind of thing). Point is, I think you are getting
bed numbers by "lumping".
 

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