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[Moved] PCIe tester card design questions

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Andy Seager

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Hi,
This is my first post on this forum, so bear with me!

First some background:

I'm currently studying Electrical and Electronic Engineering and I've been tasked by my company to design a prototype PCIe card for testing PCIe connection functionality on our products. This is part of my final project for the course, which has to be work-based.
I'm not expected to test the high-speed lanes, as that would be far and above the level of my course (pre-degree). However, I'm told that it should be possible to test the power/clocks/etc.

I'm confident that I can test the power lanes, however am less sure about the clocks (REFCLK in particular). I'm planning on using a microcontroller to test the voltages, but I don't reckon that I can measure a 100MHz clock (might be a bit too fast!).
I've hit upon the idea of using a frequency divider along with a phase-lock to step down the frequency to a more readable level and possibly convert that frequency to a readable voltage.

Either that or find a CPLD that I could use to measure it instead, but that's where I hit a wall as I've never dealt with programming CPLDs before (only loaded FW to them).
Basically, I need some guidance as to whether I am heading in the right direction.

Any help would be highly appreciated!
 

Dan Mills

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Re: PCIe tester card design questions

Why the PLL?

100MHz should be easily within the range of a simple prescaler, then feed to the counter/timer input on your favourite small micro once you have it down to 10MHz or so (Maybe a /16 part would be appropriate), use a crystal for the micros clock source so it is a fairly accurate timebase.

IIRC the clock on a PCI card is LVDS? If so then there are many, many chips that provide clock division see for example https://www.micrel.com/index.php/products/clock-timing/clock-data-distribution/clock-dividers.html or TIs equivalent page.

Do not pick a part that is too fast, lest you get into major decoupling pain, you are only working at 100Mhz, so folks like pericom are probably overkill.

Regards, Dan.
 

Andy Seager

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Re: PCIe tester card design questions

Thanks for the reply Dan.

I checked the website, didn't realise there was so much available.

My reasoning behind the PLL was due to some research that suggested it when measuring the REFCLK. Maybe because it is a differential signal? I'm new to some of PCIe, so still learning.

Need to find one that can take 100MHz as an input now with a /16.
 
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