[Moved] OTA using sub threshold input diff pair

[ananthesh bhat]

Hello,

I'm trying to design a single stage OTA where the input pair will be operated in sub threshold region. I'm not aware of the methodology in sizing the transistors for this scenario. Can anybody help in this?

Any articles related to this topic?

 

[SIDDHARTHA HAZRA]

Hi ananthesh,

Generally if the gm requirement is high then the diff pairs are pushed in to sub-threshold. Also if the input common mode demands, then to keep the tail mos (current mirror mos) in saturation.
But a MOS in sub-threshold generally has higher offset than a MOS in saturation (having similar size/area).

Hope this helps ...

 

[ananthesh bhat]

Hello Siddhartha,

yes. gm will be more for the sub-threshold OTA.
I'm using it for the sub 1 V applications. My input voltage(DC voltage) for the diff pair is in the range of 500mV. At the same time, the threshold voltage is 550mV. So, obviously I need to go for sub-threshold based diff pair. But my question is, are there any design methodologies in deciding the W/L ratios?

 

[Dominik Przyborowski]

gm/Id is enough. Set your inversion coefficient equal 0.1 or less and based on specific current calculate the W/L ratio.

 

[SIDDHARTHA HAZRA]

Hello Siddhartha,

yes. gm will be more for the sub-threshold OTA.
I'm using it for the sub 1 V applications. My input voltage(DC voltage) for the diff pair is in the range of 500mV. At the same time, the threshold voltage is 550mV. So, obviously I need to go for sub-threshold based diff pair. But my question is, are there any design methodologies in deciding the W/L ratios?

Ya, you can go for gm/Id method as suggested by Dominik.
Your application is a low power application. With a Vg of 500mV and Vth of 550mV you can keep the diff pair in sub threshold with Von = -150mV. So that the VDS of the tail MOS is 100mV. You might have to keep the tail current mirror in sub-threshold as well. Again, you can use PMOS diff pair (input is ~VDD/2) as you can short body and source which will keep Vth low (if you have a twin well then its fine).

Hope this helps ...

 

[ananthesh bhat]

gm/Id is enough. Set your inversion coefficient equal 0.1 or less and based on specific current calculate the W/L ratio.

hello,

Can you please explain a bit about inversion coefficient?? any articles explaining the procedure with gm/Id?

 

[erikl]

... any articles explaining the procedure with gm/Id?

See this post.

 

[Dominik Przyborowski]

hello,

Can you please explain a bit about inversion coefficient??

Check this paper about EKV MOS model.

 

[ananthesh bhat]

See this post.

Hey Dominik,

I went through the articles you suggested. The method of deciding W/L based on the inversion coefficient is very good. But I'm little bit stuck here. I have maintained an inversion coefficient of a diode connected MOS at 0.006. I was expecting a current which is complementary to absolute temperature through this transistor. But the results are contradicting. The current flowing through the transistor is actually PTAT. How can this be possible. I have maintained a Vds > 4*(thermal voltage) also.

- - - Updated - - -

Hey Dominik,

I went through the articles you suggested. The method of deciding W/L based on the inversion coefficient is very good. But I'm little bit stuck here. I have maintained an inversion coefficient of a diode connected MOS at 0.006. I was expecting a current which is complementary to absolute temperature through this transistor. But the results are contradicting. The current flowing through the transistor is actually PTAT. How can this be possible. I have maintained a Vds > 4*(thermal voltage) also.

Hey

Sorry for the previous reply. Its my mistake. I was observing current instead of voltage. Really sorry for that.