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You need to look at this very carefully. Make sure
that the comparison is at similar "overdrive" (VT+V)
and not at similar Vgs, where (say) the low-VT FET
is in weak inversion or even "on", and the high-VT
is "off". They should be operated at equal-gm points
and equal current density (you may or may not see
both at once) to make a valid comparison.
In SOI I have seen grossly different RTN signatures,
where the low- and medium-VT FETs were fully
depleted and the high-VT FETs were not; a stark
kink in the ID-VD curve when operated near-threshold
and a lot of exposed, noise-active states at the back
interface which were under "gate authority" in the FD
(low-VT) devices, but not so for the quasi-PD high VT
So too, a low channel doping may let the low-VT
FETs' intrinsic "front gate" surface states cause more
low frequency noise activity while high VT implant
can mask or bury these (although every implant also
adds defectivity -> states). Some high VT FETs can
be "buried channel" and mask much gate ox trap
So now you have a few (potential reasons). And
what does this (potential) knowledge do for you?
Probably not much. In the end you have to ride
the horse you picked. Or had picked for you.
Yes, you are right, they should be compared with the same Vov voltage.
I just use the same Vgs to bias the high Vth and low Vth transistor, and then observe the thermal noise in the current mirror configuration from them.
The thermal noise equation is: in^2=KT*(gm)/3. For the low Vth device has higher Vov, with the same Vgs bias condition, which leads to larger gm, so the low Vth CMOS has "higher" thermol noise in the current mirror configuration.
If they are with the same Vov, the thermal noise should be the same.