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[Moved]: MASH 1-1-1 ( sigma delta modulator) Verilog A model

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NikosTS

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Hello all,

I want to design a model of a MASH 1-1-1 ( 3rd order sigma delta modulator) in Verilog A.
I am new to VerilogA and i am having trouble designing it, especially the delays of the error cancellation network.
Any help will be greatly appreciated.

Thank you in advance
 

pancho_hideboo

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Re: MASH 1-1-1 ( sigma delta modulator) Verilog A model

If you use Cadence dfII, you can find samples in $CDS_TOP_DIR/IC/tools/dfII/samples/artist/pllMMLib.

BTW, I don't use them since I can writer more good models by myself.
 

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