[Moved]: Low ESL output capacitor for LDO

[JZJIANG]

Hi,

I've just designed an LDO which requires a low ESL output capacitor (1~4.7uF) to offer high PSRR at high frequencies and good transient response.

I have completed the preliminary testing with a stacked SMD MLCC capacitor (4.7uF with a resonant frequency at ~1MHz), can anyone give some comments on this type of capacitor?

It seems that the three terminal feedthrough capacitor can achieve a much higher resonant frequency (~8MHz for 4.7uF capacitor). However, the feedthrough capacitor is typically used as bypassing capacitor, my question is, can it be used as the output capacitor of LDO?

There are also other types of low SEL capacitor such as the reversed geometry capacitor, and the multiple-terminal capacitor, etc. Anyone have ever used these capacitors, or have any comments on these capacitors?

Thank you in advance.

 

[FvM]

Re: Low ESL output capacitor for LDO

I doubt that achieving low LDO output capacitor impedance > 1 MHz is a useful task. It would be only useable at the LDO location but not at the load. You better use multiple distributed bypass capacitors.

PSRR is a different thing. If you expect high frequency interferences, e.g. from a preceding switch mode regulator, low ESL capacitors or "feedthrough" may be helpful. Much more effective is however a LC filter.

Besides this considerations, any of the discussed special bypass capacitor types serves it's purpose. From a BOM minimization viewpoint, it's often preferred to use multiple standard MLCC capacitors in parallel, the smaller the better.