The firs thing that comes to mind is two NOR gates in the same arrangement as done with an SR flip-flop to store trigger commands. Had you already performed some mental simulation with that kind of circuit ?
The firs thing that comes to mind is ...............an SR flip-flop to store trigger commands. Had you already performed some mental simulation with that kind of circuit ?
That is where I get lost................ The 1st thing that came to mind was a flip-flop which I know in vague conceptual terms, but not in real world terms
At least as far as I can see, the S and R signals at the truth table in that link seems like depicting exactly what you want to do with input_1 and input_2 NOT'ed.
Sorry, I should have stated that the left-hand switch was closed previously. This causes the right-hand transistor to conduct.
The transistors are interlocked. When one transistor turns on, it shuts off the other. They maintain a state until you disrupt the bias on a transistor. Thus the circuit is stable.
Notice that a small signal is able to cause a change of state in the circuit.
This instructable tutorial has logic gates made from NPN BJTs, they all work correctly, I repeated them all with logic level NMOS and they worked just as well. You may need to adjust some resistor values to ensure correct latching.
While NMOS isn't as good as CMOS, they are quick and functional schematics to follow, and don't use a large amount of transistors, "large amount" relatively speaking, of course.
CMOS ones seemed hard to get to work properly, but there are many reliable resources, tutorials and schematics on the Internet to browse through.
Unless you especially want to make one using discrete components, I'd just buy any of the many SR latch ICs available, saves space and PCB design, component count and cost...