[moved] import veriloga model into cadence

[Nikhita Baladari]

Reference existing thread

https://www.edaboard.com/threads/267995/

I am facing a similar problem. I want to model a cntfet in cadence using veriloga. I used the veriloga code (https://nano.stanford.edu/stanford-cnfet-model-verilog). I followed these steps to create the cntfet model-

1. I created a new veriloga cell view and edited the veriloga.va by copying the code of NCNTFET_L3.va. I also added the fles NCNFET_L2.va, NCNCNT_L3.va and parameters.vams in the veriloga directory created.

2. I created a symbol from the veriloga cell view (create->cellview->from cellview).

3. Now I opened a new schematic and used this symbol to implement a simple circuit. I was not able to select from schematic for plotting the outputs and encountered the error -

ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be corrupt or may not be produced at all.

To generate correct netlist, fix the errors and re-netlist.
...unsuccessful.

What and where could be the problem? Kindly look into this and help me out.

 

[erikl]

What and where could be the problem?

If netlisting didn't succeed, you should show your veriloga.va code.

 

[sudeep_]

If netlisting didn't succeed, you should show your veriloga.va code.

Extract the veriloga code without any errors. Create a testbench with config file.

 

[dick_freebird]

You should at least push down into the veriloga view from
the schematic one time. This will open the view in an editor
tool, and saving will then kick off the syntax checking and
make the veriloga recognized. Doing this outside the design
system will not have the same effect.

You also need to have veriloga in your switch-view and
stop-view lists, and to have precedence (by position, in
said lists) over any other views that exist. Or use the
hierarchy editor (start sim from config view rather than
schematic) so you can assert the desired representation.

 

[Nikhita Baladari]

Thanks a lot for the help.

I got rid of that error. But I am encountering this error:

Internal error found in spectre during hierarchy flattening, during circuit read in......

FATAL (SPECTRE - 18): Segmentation fault.

I tried changing the switch and stop view lists to "spectre cmos_sch cmos.sch schematic veriloga" but in vain. If this is not correct please tell me what should be done.

Also can someone tell me what model file should be selected for the model library.

Should I change/set any other options in the "Setup" in ADE?

 

[sudeep_]

Stop view list should be either spectre or symbol.

 

[dick_freebird]

No, if you want the veriloga then stop list has to include
veriloga, and veriloga has to be picked up before any other
alternate existing view. Or, use Hierarchy Editor and a
config-view based simulation.

Now segmentation fault should not be an outcome of a
normal netlisting or simulation run. You might have some
kind of installation problem, there.