[moved] Implementing I2C on Spartan3E FPGA

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity i2c_eeprom is

    Port ( clk : in  STD_LOGIC;
           scl : out  STD_LOGIC;
           sda : inout  STD_LOGIC);
			  
end i2c_eeprom;

architecture Behavioral of i2c_eeprom is

signal counter : integer:=0;
signal state   : integer:=0;
signal delay   : std_logic:='0';

signal data    : std_logic_vector(7 downto 0):=x"41";	-- Data to be write into the EEPROM
signal slave_addr : std_logic_vector(7 downto 0):=x"A0";-- Slave address and which indicates data is going to write on EEPROM
signal internal_addr : std_logic_vector(7 downto 0):=x"00";-- Internal address of EEPROM to store the data
signal i : integer:=7;

begin

process(clk)
begin
	if rising_edge(clk) then
		counter<=counter+1;
		if counter=119 then			-- Total count for 100 KHz
			counter<=0;
			delay<=not delay;
		end if;
	end if;
end process;

process(delay)
begin
	if rising_edge(delay) then
	
		state<=state+1;
		case state is
----------------------------- Start condition--------------------			
			when 0=>	
						scl<='1';	
						sda<='1';
						
			when 1=>
						sda<='0';
						
			when 2=>
						scl<='0';
			
------------------------ Sending slave address ie.) x"A0"---------------------------------------------

			when 3=>
						sda<=slave_addr(i);	
						scl<='1';
						
			when 4=>
						scl<='0';
						
						if i=0 then
							i<=7;
							state<=5;
						else
							i<=i-1;
							state<=3;
						end if;
						
			when 5=>
						scl<='1';				-- Checking ack
						
			when 6=>
						scl<='0';
						
--------------------	 Sending internal address ie). x"00"-----------------------------

			when 7=>
						sda<=internal_addr(i);
						scl<='1';
						
			when 8=>
						scl<='0';
						
						if i=0 then
							i<=7;
							state<=9;
						else
							i<=i-1;
							state<=7;
						end if;
						
			when 9=>
						scl<='1';	-- Checking ack
						
			when 10=>
						scl<='0';
						
--------------------- Sending data 'A' ie). x"41" --------------------

			when 11=>
						sda<=data(i);
						scl<='1';
						
			when 12=>
						scl<='0';
						
						if i=0 then
							i<=7;
							state<=13;
						else
							i<=i-1;
							state<=11;
						end if;
						
			when 13=>
						scl<='1';		-- Checking ack
						
			when 14=>
						scl<='0';
						
-------------------------- Stop condition ----------------------------------------

			when 15=>
						sda<='0';
						scl<='1';
						
			when 16=>
						scl<='1';
						sda<='1';
						
			when 17=>
						scl<='0';
						
			when others=>
			
		end case;
	end if;
end process;
						
end Behavioral;