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#### Prameeth

Hi

##### Super Moderator
Staff member
As I suspect this is homework, I won't just give you the answer, but will instead try to help you realize what you should be looking at to figure this out on your own.

• How many inputs does a half adder have?
• What does the half adder do with it's input bits?
• How many inputs does a full adder have?
• What does the full adder do with all it's input bits?
Now answering those questions it should be easy to see how you can use half adders to make a full adder.
--- Updated ---

I'm also moving this to the Elementary Electronics section as I highly doubt this is being implemented in an ASIC or needs ASIC tools to do.

#### Prameeth

##### Newbie level 4
So I am able to implement the sum by just cascading 2 half adders, but then won't we require at least an or gate for implementing carry?
S=A xor B xor C ( all I need to do is connect output of one half adder as one of inputs to other while other being Cin)
But for carry Cout=AB+Cin(A xor B)
(Or)
Cout=AB+BCin+ACin
We do need an or gate right? As my half adder only implements xor, and gate. But I need to OR gate values for Cout.

#### KlausST

##### Super Moderator
Staff member
Hi,

It's not clear to me how your solution looks like. Show your design.

Klaus

##### Super Moderator
Staff member
So I am able to implement the sum by just cascading 2 half adders, but then won't we require at least an or gate for implementing carry?
S=A xor B xor C ( all I need to do is connect output of one half adder as one of inputs to other while other being Cin)
so far you're doing great!

But for carry Cout=AB+Cin(A xor B)
(Or)
Cout=AB+BCin+ACin
We do need an or gate right? As my half adder only implements xor, and gate. But I need to OR gate values for Cout.
You've cascaded the half adders. The AB_sum and AB_cout are the outputs of the first half adder.

You took the AB_sum + Cin and got an ABCin_sum and ABCin_cout.

So you now have two different carries AB_cout and ABCin_cout. Don't these both have information on what the carry should be for the cascaded half adders?
--- Updated ---

Just to make it clear what circuit Prameeth and I are discussing

Code Verilog - [expand]1
2
3
4
half_adder  ha1 (.s (sum_ab), .c(cout_ab), .a(a), .b(b));
half_adder  ha2 (.s(sum_abci), .c(cout_abci), .a(ci), .b(sum_ab));
// sum_abci is the correct sum as Prameeth has determined in post #3
// but what should be done with the signals cout_ab and cout_abci?

Last edited:

I got it right
Thank you

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##### Super Moderator
Staff member
Exactly.

Did you notice that you don't need an OR gate (as your thought in post #3)? What you needed was an XOR gate to finish computing the carry calculation as the two carry bits can only be 00, 01, or 10 with a 0 or 1 resulting sum (with no new carry).

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