[Moved]: I want to use a smaller MOSFET than 65nm for Hybrid SET/CMOS simulation

[Manolis Grifoman]

Hello! I designed a hybrid circuit consisting of MOSFET and Single Electron Transistors. For this, I used the model BSIM4.8.0. 65nm. I want to use a "smaller" transistor. So, I found one... At least, a hypothetical one... The PTM 45nm. The problem is... In the parameters i find: Level=54. So, I take an "empty" transistor from the pspice library breakout, the MbreakP (let's assume I need pmos). Now... When I copy paste the parameters, it pops an error in simulation. An error regarding the level in the parameters. So i change it from level 54 to level 9. Does it make any significant difference? And if so, what "empty" model from the breakout library should I use to succesfully simulate the PTM of level 54? (Also, can you propose any transistor models below 65 nm technology and give me the txt with the parameters?) Thank you very much in advance.

 

[erikl]

... So i change it from level 54 to level 9. Does it make any significant difference?

I think so: AFAIK, level 9 models are either VBIC99 (Motorola) or AMD-specific MOSFET models, s. pp. 215 & 457 of the foll. document: View attachment Avant_True-Hspice_Device_Models_Reference Manual_2001.4.pdf

 

[Manolis Grifoman]

Thank you for the information! Do you know maybe what "empty" transistor model can I use from breakout so I can simulate the lvl 54 transistors correctly?