Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
First you would take the 5kVA to a power switch dissipation.
This needs either direct measurement, simulation or a power
and efficiency calculation. Not knowing any design details
I'd use an 80% full load efficiency and this would roughly
mean 1kW losses in the powertrain. Figure a minimal bridge
inverter ought to apportion those losses roughly evenly
(though details could skew that apportionment) to 250W
in each of the 4 bridge FETs (this is an H-bridge output,
right?).
Now look to your thermal path and its worst casing -
airflow, inlet air temp, air-to-baseplate heat sink figure
of merit (degC/W), baseplate to junction on the FETs
and the tolerable junction temperature for your desired
reliability. From this you can get at the temp rise for
that 250W. If it's exceeding your target junction temp,
this is where you start throwing bodies at the problem
(parallel FETs, divide temp rise by N more or less).
You would probably benefit by doing this in a spreadsheet
so you can work the tradeoffs (such as different heat sink,
different FETs' loss mechanisms / values, etc.). Probably
starting with a bottom up model of those losses is good,
it may even help you with component selection what-if-ing.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
