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[Moved] Error while compiling VHDL code in Xilinx software

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Arrowspace

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I am getting this error

ERROR:Xst:841 - "H:/Carry increment/carryincrement/carryincrement.vhd" line 98: Bad condition in wait statement, or only one clock per process.

2.JPG
 

That is testbench code, and the error indicates you are trying to synthesise it (which you cant) or there is no wait statement in the process.

I cant see all the code - is there a wait statement?
 
On their is no wait statement in process

- - - Updated - - -

where should i use wait statement ?
 

Assuming you're only simulating it - somewhere appropriate in the process.

In simulation, processes without a sensitivity list loop forever in 0 time. You need a wait statement to make it wait to move the time forward.
 

Arrowspace, you should just post your code instead of using screen captures. Then members can look at what you are doing in the proper context, instead of making guesses.
 

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