thanks for the reply FvM.
Thanks for the reply pancho_hideboo, but What is "pIIMMLib" which library is this??
Thanks for the reply asdf44,
Please see the image attached with this reply,
https://obrazki.elektroda.pl/9756054400_1486740617.png
This is a second order sigma-delta modulator (all blocks are ideal verilogA models only) schematic design, problems with this is:
1. Although there is a negative feedback, the output of the integrator is very high in kVs due to which the ADC (4-bits) always give logic 1 and corresponding the DAC (4-bits) output is Vmax (= 1.8 V in this case).
2. If we use all the blocks of the schematic except the integrator the system works perfectly fine (i.e ADC, DAC, Sample&Hold and vcvs blocks work fine).
3. The input signal is 200 mV (peak-peak) and frequency = 22 kHz, while the sampling clock is operating at 2.8 MHz.