[Moved]digital system to detect a pulse

[sun_ray]

Please provide a digital system or circuit to detect a pulse.

 

[FvM]

To avoid further inquiries, you should by all means clarify the context of your question or explain what you want to achieve.

 

[jiripolivka]

Without any details it is not possible to "provide a digital system".

Pulse detectors generally use comparators.

 

[ads-ee]

Here's a "digital system" to detect a pulse:

 

[sun_ray]

Can anybody please help to provide a digital circuit to detect a pulse where the pulse is being used as the input of the clock pin of a D flipflop?

Regards

 

[TrickyDicky]

Can anybody please help to provide a digital circuit to detect a pulse where the pulse is being used as the input of the clock pin of a D flipflop?

Regards

Probably not, as that would be bad practice inside an fpga

How about giving us some of the specs and slow is what you've done already.

 

[mrflibble]

Can anybody please help to provide a digital circuit to detect a pulse where the pulse is being used as the input of the clock pin of a D flipflop?

Sure. See ads-ee's reply, with the addition of a constraint to suppress synthesis warnings.

How about giving us some of the specs ...

This.

 

[FvM]

The problem is the lack of any specification in the original post, resulting in the slighty ironical but technical correct answers...

If you are e.g. looking for a circuit that can detect an asynchronous pulse of variable width (shorter or longer than the system clock) you should read about toggle synchronizers.

 

[arishsu]

Please provide a digital system or circuit to detect a pulse.

Here is a single code to detect a pulse. You can easily figure out the circuit from the code. This circuit actually detect the changes in the input 'in'. 'in' is normally tied to 'high' and if it produces a low pulse, the output of the circuit gives a single pulse. This is actually a Fall Edge Detector(FED).
I don't really understood what it meant by 'pulse detector'. Hope this is helpful.

module FED(in,clk,out);
input in,clk;
output out;
wire q0,q1;
D_FF D1(in,clk,q0),
	  D2(q0,clk,q1);
assign out=(q0 && !q1);
endmodule

module D_FF(d,clk,q);
input d,clk;
output reg q;
always@(negedge clk)
 begin
  q<=d;
 end
endmodule