[MOVED] DAC area saving topologies, and noise

[a991852]

Hi All,

I'm trying to make a DAC with less area using MiM Capacitors

Basically Split DAC uses less area than a binary weighted capacitors since for a 6 bit split DAC, only area of 2 3-bit DAC are required, drastically reducing area.

Split DAC (6-bit DAC):
1C
1C
2C
4C

1C
2C
4C

Binary Weighted DAC (6-bit DAC):
1C
1C
2C
4C
8C
16C
32C

However, has anyone implemented a binary weighted DAC with half of the capacitors in series and half of the capacitors in parallel?

Then the binary weighted DAC would have almost the area compared to a split bridge DAC:
1/8C
1/8C
1/4C
1/2C
1C
2C
4C

We also can implement the idea on a split bridge DAC, which can lower the area even further.

Does anyone know affects of serial with parallel capacitors in the circuit compared to a only parallel capacitance? I've actually implemented both types (Serial with Parallel capacitors VS only parallel capacitors) on TSMC 180nm for a 12-bit DAC, even though area was only 30% of before, BUT the ENOB of serial capacitors with parallel capacitors decreased about 1 (reduced to 10 from 11) compared to a fully parallel capacitance, I'm assuming that parasitic capacitance affects serial capacitors such as adding a capacitor between each capacitors, and more capacitance are added to parallel capacitors. Hence the actual value of parallel capacitors are GREATER than serial capacitors.

Also is noise on a capacitor DAC important? According to https://en.wikipedia.org/wiki/Johnson–Nyquist_noise

Using large number of 20f capacitors can give a few mV of noise, should I implement an auto-zeroing circuit on the DAC?

Thanks all!