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[Moved] Comparator offset cancellation

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Majid_Vatan_Parast

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Hello everybody
I need to remove the offset of a comparator, but I have problem understanding the timing of offset cancellation and routine operation of the comparator.
Can anyone help me please 😭😭
It is urgent
Please help me 😥😥
 

Hi,

is your problem related to an actual circuitry or a theoretical/assignment question?

Are you using an opamp or a dedicated comparator?
Single supply or dual supply?
IC part number?
Inverting or non-inverting?

BR
 

Speed ?
Latency/delay ?
Noise (eg. use hysteresis) ?
Absolute accuracy you are seeking ?


Regards, Dana.
 

Can anyone help me please 😭😭
It is urgent
Please help me 😥😥
Give useful informations, first.

What circuit, how and why?
What has "offset" to do with "timing"?

Give descriptions, links, pictures - even hand drawn....

Klaus
 

Where / how you would "hide" the autozero depends on
the application externalities as well. A continuous-time
comparator with no clock resource would be tricky and
probably involve a pair of comparators plus switches
for the signal path, in addition to the zeroing "stuff". A
clocked comparator is easier, and there's a ton of
papers on CMOS comparators of that sort. Academia.edu
has a lot of that kind of thing.
 

Hi,

is your problem related to an actual circuitry or a theoretical/assignment question?

Are you using an opamp or a dedicated comparator?
Single supply or dual supply?
IC part number?
Inverting or non-inverting?

BR
Hi
It is an actual circuitry, I am designing a 2b/c SAR ADC. It is a dynamic comparator with single supply. I want to implement a current mode offset cancellation circuitry.
Do I need to perform offset cancellation in every cycle ( every T ) or it is done only once?
When offset cancellation should start and when stop?
U can see structure of the comparator and Cks & Ck signal in the picture below.
--- Updated ---

Give useful informations, first.

What circuit, how and why?
What has "offset" to do with "timing"?

Give descriptions, links, pictures - even hand drawn....

Klaus
Hi
Offset cancellation circuit needs some control signals to work, I need to know the timing of these control signal in comparison with comparator and sampling clock.
And more important question, Do I need to perform offset cancellation in every cycle ( every T ) or it is done only once in entire ADC operation ?
By the way I am designing an asynchronous 2b/c SAR .
 

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Last edited:

Hi,

so you are doing "IC design" but posted in the "Analog Circuit Design" ... this explains the confusion.
I´ll move this thread to IC-Design section.

Klaus
 

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