word0 word1 word2 word3
f1| | | |
f2 | | | |
word0 word1 word2 word2
a long FIFO would only postpone the inevitable loss of data. So you're going to lose data, but if you already know that and the system design is okay with the data loss then that shouldn't be an issue.I don't have other option without usng long FIFOs and hoping both frequencies average to the same value before the FIFO gets empty/full, correct?
The problem is a small size CPLD will probably be inadequate, you really need to perform clock domain crossing on control signals, which means you have to buffer too much data for a small CPLD. You will likely need at least 4 words of storage given the 2 FF synchronizers and all the control logic that a FIFO would normally have to pass the addresses between domains.So on your question.
Yes I am OK to skip or double data word once in a while but I want to get consistent data at f2.
I mean I want to be sure all data at f2 are correct data which have been available at f1 at certain moment.
I want to be metastable free.
Thaking this into account do you think this can be implemented in a small size CPLD?
Do you have recomendations in this respect?
I see this as very possible.
Let's call FSC1, FSC2 for framesyncs and CLK1 and CLK2 for clocks. I see a HW doing this:
1) 2x shift-registers (CLK1/CLK2), 2x counters from 0 to 15 (CLK1/CLK2). When FSC1/FSC2 edge is detected, data is stored on shift registers using the counters.
2) Once the counter goes to 0 again, you move the data from shift register to a buffer (in both cases, meaning 2x 16-bits buffer).
3) When FSC2/FSC1 is detected (note you are on opposite clock domain now), you read the data from buffers, serialize it (2x shift registers(CLK2/CLK1) + 2x counters (CLK2/CLK1) again) and send the data.
If you had a FPGA, a BRAM could be used - it can work with two clocks domains easily.
Well both PCMs has a separate data_in and data_out wire so it is full duplex comunication.I'm not sure from your description, how both master devices can write to each other, who decides which one writes to the other one? What part is this, so I can look at a datasheet?
The OP doesn't say this is serial or parallel. I thought about double buffering, but there could be issues with drifting clock phase. Neither clock is locked to the other, I'm assuming the device generates it's own clock. So you could run into meta-stability issues if the end of the shift and transfer from say FSC1 updating the buffered register (that FSC2 reads) right at time when FSC2 has a rising edge then you could end up with a meta-stable event.
Hi pbernardi,
What will happen if FSC2 occurs at the same time with FSC2? So the check for " no transfer is being done" should be done in CLK1 domain but is set in the CLK2 domain.
But probably I can set the 'Transmission flag' (you are talking about ) one CLK2 before the actual trasfer. (I can do that because I know that I have 32 CLK2 periods between each FSC2)
What you Gents thing, it will work?
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