library IEEE;library std;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
--use std.env.all;
entity testbench is
end testbench;
architecture Behavioral of testbench is
file data:text open write_mode is "data.txt";
COMPONENT blk_mem_pic23_9bit
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
--inputorary signal declarations for bram_test.
signal ena : std_logic;
signal wea : std_logic_vector(0 downto 0);
signal dina : std_logic_VECTOR(8 downto 0);
signal douta : std_logic_VECTOR(8 downto 0);
signal addra : std_logic_VECTOR(14 downto 0);
signal clk : std_logic;
begin
--Instantiating BRAM.
bram : blk_mem_pic23_9bit
port map(
clka => clk,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
--Simulation process.
bram1 : process
variable temp,temp1 : std_logic_vector(8 downto 0);
type mat is array(0 to 8) of std_logic_vector(8 downto 0);
variable value:mat;
variable dil,depth : integer := 1;
variable count: integer := 0;
variable carry : std_logic := '0';
variable carry_fwd : std_logic := '0';
variable txt:line;
begin
ena <='1';
wea <= "0";
dina <= "000000000";
value(8) := "000000000";
addra <= "000000000000000";
for dil in 1 to 4 loop
for depth in 0 to 25600 loop
wea <= "0";
temp := douta;
for count in 0 to 8 loop
if (count = 0) then
if (temp(count) = '1') then
temp1(0) := temp(0) and '1';
temp1(1) := temp(1) and '1';
temp1(3) := temp(3) and '1';
temp1(4) := temp(4) and '1';
value(0) := "000011011";
elsif (temp(count) = '0') then
temp1(count) := '0';
value(0):= value(8)+"000000000";
end if;
elsif (count = 1) then
if (temp(count) = '1') then
--temp1 := temp(0)*1+temp(1)*1+temp(2)*1+temp(3)*1+temp(4)*1+temp(5)*1;
temp1(0) := temp(0)and'1';
temp1(1) := temp(1)and'1';
temp1(2) := temp(2)and'1';
temp1(3) := temp(3)and'1';
temp1(4) := temp(4)and'1';
temp1(5) := temp(5)and'1';
value(1) := "000111111";
elsif (temp(count) = '0') then
temp1 := value(0)+"000000000";
value(1):= "000000000";
end if;
elsif (count = 2) then
if (temp(count) = '1') then
--temp1(count) := temp(1)*1+temp(2)*1+temp(4)*1+temp(5)*1;
temp1(1) := temp(1)and'1';
temp1(2) := temp(2)and'1';
temp1(4) := temp(4)and'1';
temp1(5) := temp(5)and'1';
value(2) := "000110110";
elsif (temp(count) = '0') then
temp1 := value(1)+"000000000";
value(2):= "000000000";
end if;
elsif (count = 3) then
if (temp(count) = '1') then
--temp1(count) := temp(0)*1+temp(1)*1+temp(3)*1+temp(4)*1+temp(6)*1+temp(7)*1;
temp1(0) := temp(0)and'1';
temp1(1) := temp(1)and'1';
temp1(3) := temp(3)and'1';
temp1(4) := temp(4)and'1';
temp1(6) := temp(6)and'1';
temp1(7) := temp(7)and'1';
value(3) := "011011011";
elsif (temp(count) = '0') then
temp1 := value(2)+"000000000";
value(3):= "000000000";
end if;
elsif (count = 4) then
if (temp(count) = '1') then
--temp1(count) := temp(0)*1+temp(1)*1+temp(2)*1+temp(3)*1+temp(4)*1+temp(5)*1+temp(6)*1+temp(7)*1+temp(8)*1;
temp1(0) := temp(0)and'1';
temp1(1) := temp(1)and'1';
temp1(2) := temp(2)and'1';
temp1(3) := temp(3)and'1';
temp1(4) := temp(4)and'1';
temp1(5) := temp(5)and'1';
temp1(6) := temp(6)and'1';
temp1(7) := temp(7)and'1';
temp1(8) := temp(8)and'1';
value(4) := "111111111";
elsif (temp(count) = '0') then
temp1 := value(3)+"000000000";
value(4):= "000000000";
end if;
elsif (count = 5) then
if (temp(count) = '1') then
--temp1(count) := temp(1)*1+temp(2)*1+temp(4)*1+temp(5)*1+temp(7)*1+temp(8)*1;
temp1(1) := temp(1)and'1';
temp1(2) := temp(2)and'1';
temp1(4) := temp(4)and'1';
temp1(5) := temp(5)and'1';
temp1(7) := temp(7)and'1';
temp1(8) := temp(8)and'1';
value(5) := "110110110";
elsif (temp(count) = '0') then
temp1 := value(4)+"000000000";
value(5):= "000000000";
end if;
elsif (count = 6) then
if (temp(count) = '1') then
--temp1(count) := temp(3)*1+temp(4)*1+temp(6)*1+temp(7)*1;
temp1(3) := temp(3)and'1';
temp1(4) := temp(4)and'1';
temp1(6) := temp(6)and'1';
temp1(7) := temp(7)and'1';
value(6) := "011011000";
elsif (temp(count) = '0') then
temp1 := value(5)+"000000000";
value(6):= "000000000";
end if;
elsif (count = 7) then
if (temp(count) = '1') then
--temp1(count) := temp(3)*1+temp(4)*1+temp(5)*1+temp(6)*1temp(7)*1+temp(8)*1;
temp1(3) := temp(3)and'1';
temp1(4) := temp(4)and'1';
temp1(5) := temp(5)and'1';
temp1(6) := temp(6)and'1';
temp1(7) := temp(7)and'1';
temp1(8) := temp(8)and'1';
value(7) := "111111000";
elsif (temp(count) = '0') then
temp1 := value(6)+"000000000";
value(7):= "000000000";
end if;
elsif (count = 8) then
if (temp(count) = '1') then
--temp1(count) := temp(4)*1+temp(5)*1+temp(7)*1+temp(8)*1;
temp1(4) := temp(4)and'1';
temp1(5) := temp(5)and'1';
temp1(7) := temp(7)and'1';
temp1(8) := temp(8)and'1';
value(8) := "110110000";
elsif (temp(count) = '0') then
temp1 := value(7)+"000000000";
value(8):= "000000000";
end if;
end if;
end loop;
--wait for 2ns;
wea <= "1";
dina <= value(0) or value(1) or value(2) or value(3) or value(4) or value(5) or value(6) or value(7) or value(8);
if(wea = "1") then
write (txt,dina);
writeline(data,txt);
end if;
wait for 2ns;
wea <="0";
addra <= addra + "1";
if (addra = "110010000000000") then
addra <= "000000000000000";
end if;
end loop;
end loop;
report " Simulation finished";
wait;
end process bram1;
--Clock generation - Generates 500 MHz clock with 50% duty cycle.
process
begin
clk <= '1';
wait for 1ns; --"ON" time.
clk <= '0';
wait for 1ns; --"OFF" time.
end process;
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