Hello all,
regarding setup/hold time of a logic cell (ex. DFF)...In case of input logic '1', is the definition of setup/hold time is that input should be constant (voltage wise not logic wise) during this time or generally greater than cell threshold voltage ? (so maybe varying but still above cell threshold)
for standard cell characterization, Vth is not taken into account like that. setup is with respect to signals transition full swing, from 0 to VDD, not from 0 to Vth.
You need to generate a new .lib file, which can be quite complicated. Some spice-like simulations can help you fake a .lib file, assuming both VDD and Vth are the same value. No need for design modification, just set the voltage levels accordingly on the spice simulation. Results, however, can be very poor. There's a reason digital design doesn't operate in deep subthreshold.
A designer should not change the transistor model, not
unless he has control over the process and plenty of
time to wait.
Unless you have no intention of delivering a real and
functioning product, then lie all you want about what
the transistors are like.
.subckt DFF_X1_2 D CK QN VSS VDD Q
M_MN2 ci cni VSS VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN6 VSS z4 z6 VSS NMOS_victim L=5e-08 W=9e-08
M_MN7 z3 ci z6 VSS NMOS_victim L=5e-08 W=9e-08
M_MN4 z2 cni z3 VSS NMOS_victim L=5e-08 W=2.75e-07
M_MN3 z2 D VSS VSS NMOS_victim L=5e-08 W=2.75e-07
M_MN5 z4 z3 VSS VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN1 VSS CK cni VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN8 z12 z3 VSS VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN9 z9 ci z12 VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN12 z9 cni z8 VSS NMOS_victim L=5e-08 W=9e-08
M_MN11 z8 z10 VSS VSS NMOS_victim L=5e-08 W=9e-08
M_MN10 VSS z9 z10 VSS NMOS_victim L=5e-08 W=2.1e-07
M_MN14 QN z9 VSS VSS NMOS_victim L=5e-08 W=4.15e-07
M_MN13 VSS z10 Q VSS NMOS_victim L=5e-08 W=4.15e-07
M_MP2 ci cni VDD VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP6 VDD z4 z1 VDD PMOS_victim L=5e-08 W=9e-08
M_MP7 z1 cni z3 VDD PMOS_victim L=5e-08 W=9e-08
M_MP4 z3 ci z5 VDD PMOS_victim L=5e-08 W=4.2e-07
M_MP3 z5 D VDD VDD PMOS_victim L=5e-08 W=4.2e-07
M_MP5 z4 z3 VDD VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP1 VDD CK cni VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP8 z7 z3 VDD VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP9 z9 cni z7 VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP12 z9 ci z11 VDD PMOS_victim L=5e-08 W=9e-08
M_MP11 z11 z10 VDD VDD PMOS_victim L=5e-08 W=9e-08
M_MP10 VDD z9 z10 VDD PMOS_victim L=5e-08 W=3.15e-07
M_MP14 QN z9 VDD VDD PMOS_victim L=5e-08 W=6.3e-07
M_MP13 VDD z10 Q VDD PMOS_victim L=5e-08 W=6.3e-07
.ends
* Customized PTM 45nm NMOS
.model NMOS_victim nmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
* parameters related to the technology node
+tnom = 27 epsrox = 3.9
+eta0 = 0.0049 nfactor = 2.1 wint = 5e-09
+cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08
* parameters customized by the user
+toxe = 1.75e-09 toxp = 1.1e-09 toxm = 1.75e-09 toxref = 1.75e-09
+dtox = 6.5e-10 lint = 3.75e-09
+vth0 = 0.424 k1 = 0.489 u0 = 0.04698 vsat = 147390
+rdsw = 155 ndep = 2.81e+18 xj = 1.4e-08
+k2 = 0.2
* Customized PTM 45nm PMOS
.model PMOS_victim pmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
* parameters related to the technology node
+tnom = 27 epsrox = 3.9
+eta0 = 0.0049 nfactor = 2.1 wint = 5e-09
+cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08
* parameters customized by the user
+toxe = 1.85e-09 toxp = 1.1e-09 toxm = 1.85e-09 toxref = 1.85e-09
+dtox = 7.5e-10 lint = 3.75e-09
+vth0 = -0.383 k1 = 0.457 u0 = 0.00496 vsat = 70000
+rdsw = 155 ndep = 2.2e+18 xj = 1.4e-08
+k2 = -0.2
I think you are way way way off target here. setup and hold are characteristics of flops, they are not in the netlist. Whatever you removed, I think that is part of the flop and should be put back. Go check with the documentation what the meaning of AD/AS/... is. I am almost sure that is drain area.
Setup/hold are architecture dependent.
If I understand correctly what you are doing, all you need to do is to increase the crosstalk cap. The glitch height will be higher and then it can have change to be latched in.
It would be valid to run a series of coupling cap values
to determine a layout coupling margin. Likewise valid
to vary VIH / VIL to determine an as-laid-out noise
margin. This may be your likeliest way to "weaken"
the flip-flop (internal device attributes would vary
only with a pretty constrained range, and only the
front end of the clock fork matters to this exercise.
Yes for sure, but since this simulation models a part of a VLSI physical layout that I already made, so I'm bound in this case with a minimum separation-gap/coupling-length between aggressor and victim, so I still can increase coupling capacitance but not too much.....so it would be much easier for me to weaken the DFF to accept this crosstalk voltage.
Thanks for your reply
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