Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] mosfet totem pole voltage

Zak28

Advanced Member level 2
Joined
Aug 19, 2016
Messages
579
Helped
6
Reputation
12
Reaction score
6
Trophy points
18
Activity points
4,681
Is it safe to use a PMOS with a lower Vds than its NMOS counterpart?

It seems only the NMOS counterpart interacts with the high voltage and the PMOS would be unharmed in this circuit.

 

barry

Advanced Member level 5
Joined
Mar 31, 2005
Messages
4,858
Helped
1,068
Reputation
2,146
Reaction score
1,053
Trophy points
1,393
Location
California, USA
Activity points
26,510
If you turn that pot all the way to the end, you’ll have 48 volts on the PMOS source.

Actually, upon closer examination, that PMOS will NEVER turn on.
 
  • Like
Reactions: Zak28

    Zak28

    points: 2
    Helpful Answer Positive Rating

Zak28

Advanced Member level 2
Joined
Aug 19, 2016
Messages
579
Helped
6
Reputation
12
Reaction score
6
Trophy points
18
Activity points
4,681
That is a hazard which can be removed with a series resistor to the pot or using a voltage divider instead of the pot.

But the question was whether the PMOS is completely absent of any high voltage transients which can damage it.
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
17,448
Helped
3,939
Reputation
7,876
Reaction score
3,812
Trophy points
113
Activity points
115,691
Hi,

Is it safe to use a PMOS with a lower Vds than its NMOS counterpart?
A Mosfet does not know about it's counterpart, a Mosfet dies not know about GND potential (as long as none of the three legs is directly connected to GND), it just sees the voltage differences between it's three pins. That is what you have to take care about.

Now you talk about transients:
Don't be afraid of using capacitors. They will help to reduce transients. Use them to stabilize the input powrr supply, the gate voltage and the output voltage.

Transient voltages - because of their HF nature- will be divided by the HF impedance.
Thus it mainly will depend on the (not shown) capacitance between D and S of the Mosfets ... and the stray impedance of the PCB layout.

A zener across the pot (with series impedance) will improve gate to GND voltage.
But the circuit lacks of the ability to control the output voltage. When the output voltage is i the range of V_gate (w.r.t. GND) - V_GSth of upper Mosfet ... to V_gate + V_GSth of lower Mosfet ... the output voltage is not controlled at all.
This means a range of several volts of uncontrolled output voltage.

If you want somehow controlled output voltage I recommend to use proven standard circuits...or even better: dedicated ICs.

Klaus
 
  • Like
Reactions: Zak28

    Zak28

    points: 2
    Helpful Answer Positive Rating

barry

Advanced Member level 5
Joined
Mar 31, 2005
Messages
4,858
Helped
1,068
Reputation
2,146
Reaction score
1,053
Trophy points
1,393
Location
California, USA
Activity points
26,510
I still don’t see how this circuit will do anything. In order for the bottom(PMOS) to turn on, its gate voltage has to be lower than its source. That will never happen.
 
  • Like
Reactions: Zak28

    Zak28

    points: 2
    Helpful Answer Positive Rating

Zak28

Advanced Member level 2
Joined
Aug 19, 2016
Messages
579
Helped
6
Reputation
12
Reaction score
6
Trophy points
18
Activity points
4,681
I still don’t see how this circuit will do anything. In order for the bottom(PMOS) to turn on, its gate voltage has to be lower than its source. That will never happen.
The PMOS can be logic level which would turn on at 5Vgs, also the pot was just for a reference.
 

barry

Advanced Member level 5
Joined
Mar 31, 2005
Messages
4,858
Helped
1,068
Reputation
2,146
Reaction score
1,053
Trophy points
1,393
Location
California, USA
Activity points
26,510
The PMOS can be logic level which would turn on at 5Vgs, also the pot was just for a reference.
Nope. The gate has to be five volts LOWER than the source. How is that going to happen?
 
  • Like
Reactions: Zak28

    Zak28

    points: 2
    Helpful Answer Positive Rating
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top