Emitter resistor limits the collector current and then the
G-S FET resistor can be expected to develop a fixed (-ish)
voltage. Of course there is variability w/ low side logic
signal level, BJT temp and so on.
If you wanted to peak up the current with the suggested
capacitor then there would be a gate overshoot that the
zener would have to eat once per cycle, but only after
the FET has been fully driven. The C value and the zener
pulse power limits would have to be consistent.
A commercial high side switch / load switch is of course
going to be simpler, probably cheaper, as has been
suggested. There may also be driver ICs meant for
high side switch FET gate drive, including gate
voltage regulation along with level shifting. Be sure
you pick one suited to static operation if you intend
a low switching rate, avoid bootstrap style ones in
such cases.
Hi dick_freebird,
If i put a resistor emitter to reduce the voltage to the gate, why can i remove the zener ?
It is more important the rise time of the pulse at output than fall time.
Thanks,
Doron