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Mosfet Capacitances with Negative Gate Voltage

Hi-Q

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Hey,

There are many mosfets for switching purposes, sometimes two of them conveniently packed into a single package.
Most of the times the datasheets provide data on the capacitances (Ciss, Coss, Crss) over drain to source voltage (GS shorted) and very few also provide data on the capacitances over positive gate to source voltage (DS shorted) like this one:

But I have not yet found data on the capacitances with negative gate to source voltage (talking about NMOS-FET).

I'd expect the capacitances to decrease, but I'd really like to see some data on that.

Does anyone here have some knowledge on the issue they would like to share?

Regards,
Hi-Q
 

Easy peasy

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most data sheets show C for zero Vds - this is the value to use - it is the highest ...
 

Hi-Q

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Yeah, only I don't need the highest value but the actual one with negative Vgs.
Or at least an indication on how the capacitances will behave with negative Vgs.

Will Ciss and Crss at Vds=0V and Vgs=-5V be similar to their values at Vds=5V and Vgs=0V?
Or will only Crss be similar because the voltage between drain and gate is similar, but Ciss will be different because Vgs will be -5 instead of 0V?

With Vgs=0V and Vds=5V or even 10V there is a huge difference in capacitances to Vgs=0V and Vds=0V. If this is anything similar with negative gate voltages, then the circuit may behave extremely different, for instance regarding off isolation of an analog switch built with that FET..
 

dick_freebird

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most data sheets show C for zero Vds - this is the value to use - it is the highest ...
MOSFET C-V curves are their lowest at Vgs=0 (or
close to it - depletion-mode FETs would be
slightly negative) and rise up in both inversion
(NMOS Vgs>VT) and accumulation. Both should
stop at Cox. The minimum is the depletion
capacitance in series with Cox.

Gate capacitance to S, D is overlap / fringing /
spacers in plar MOSFETs. VDMOS power FETs
will disconnect the G-D capacitance through
the "neck" at Vgs=0 and negative, connect it
with Vgs>VT. So power FETs are trickier.
 

    Hi-Q

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FvM

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The MOSFET datasheet in post #1 shows a (low) power FET. Analog switches as addressed in post #3 are symmetrical lateral FET. Their Ciss and Crss characteristics don't have the large and abrupt C variations of a power FET.
 

Hi-Q

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MOSFET C-V curves are their lowest at Vgs=0 (or
close to it - depletion-mode FETs would be
slightly negative) and rise up in both inversion
(NMOS Vgs>VT) and accumulation. Both should
stop at Cox. The minimum is the depletion
capacitance in series with Cox.

Gate capacitance to S, D is overlap / fringing /
spacers in plar MOSFETs. VDMOS power FETs
will disconnect the G-D capacitance through
the "neck" at Vgs=0 and negative, connect it
with Vgs>VT. So power FETs are trickier.
Ah, I forgot about the accumulation. Thank you, that was definitely helpful.
So it would actually be disadvantageous to apply a more negative gate bias, contrary to what would be advantageous with JFETs.

The MOSFET datasheet in post #1 shows a (low) power FET. Analog switches as addressed in post #3 are symmetrical lateral FET. Their Ciss and Crss characteristics don't have the large and abrupt C variations of a power FET.
Ok, where can I find these "symmetrical lateral FET" as discrete ones with Rds of about 1 Ohm?


Otherwise I would have to use the above kind of FET as source connected pair.
 

dick_freebird

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Ah, I forgot about the accumulation. Thank you, that was definitely helpful.
So it would actually be disadvantageous to apply a more negative gate bias, contrary to what would be advantageous with JFETs.
Depends on the application. For on-chip bulk
decoupling I would use an accumulation-mode
FET (high C, and lower Rs than the inversion
mode, where Rs is the channel on resistance).

For a signal / switch FET, you not only see C rise
with additional negative gate drive (talking
NMOS) but can also see GIDL (gate induced
drain leakage) as the drain current turns back
up after crossing a minimum near Vgs=0
(more or less; modern technologies' RVT and
LVT FETs may still be on the subthreshold slope
at Vgs=0 and see their minumum drain leakage
at some slightly negative Vgs)

This is from 45nm technology but similar stuff
goes on above or below.
1603048471059.png
 

    Hi-Q

    points: 2
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