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if i were to use MOSCAP as an on-chip decoupling capacitor , will it affects other nearby devices if it is too big? what is the good way to isolate it.
the best way is to split the MOSCAP in parallel them to have lower series resistance and more ideal ground connection, also for substrate noise reduction guard ring are used which are NWELL and P+ connection around your MOSCAP or other noisy/sensitive blocks.
Tryagain, would you pls advice what's the best ways?
We use common GND and power supply pins for analog and digital blocks, but the power lines are seperated from pads to various blocks. As for the decoupling capacitors, shall we connect them between the power supply and ground lines for the same block or any power lines is OK?
When I applied MOSCAP as the on-chip decoupling capacitors, I found that the leakage of those decoupling capacitor is an issue.
The leakages result from subthreshold one and gate tunneling one. Is it a feasible approach to apply reverse-biased junction diodes as the on-chip decoupling capacitors?
You can avoid using decoupling capacitor if space a constraint by stacking power rails on top of each other. Yau can alternate power and ground rails like interwinning fingers, that depends on metal availables in your process. This technique builds in decoupling capacistors across the power rails for f.o.c .
When I applied MOSCAP as the on-chip decoupling capacitors, I found that the leakage of those decoupling capacitor is an issue.
The leakages result from subthreshold one and gate tunneling one. Is it a feasible approach to apply reverse-biased junction diodes as the on-chip decoupling capacitors?
As leakage is your concern I suppose you're using "thin-oxide" devices in a recent technology (130nm or less).. I would not recommend the use of those devices not only because of leakage but also to avoid any robustness and high volume yield issues cause by defects in the oxide or ESD zaps.. In older technologies I've never had a problem using MOS devices as decoupling caps..
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