Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

MOSCAP as decoupling capacitor

Status
Not open for further replies.

angyp

Newbie level 5
Joined
May 18, 2004
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
130
if i were to use MOSCAP as an on-chip decoupling capacitor , will it affects other nearby devices if it is too big? what is the good way to isolate it.
 

goodboy_pl

Full Member level 5
Joined
Mar 12, 2002
Messages
253
Helped
16
Reputation
32
Reaction score
15
Trophy points
1,298
Activity points
3,119
the best way is to split the MOSCAP in parallel them to have lower series resistance and more ideal ground connection, also for substrate noise reduction guard ring are used which are NWELL and P+ connection around your MOSCAP or other noisy/sensitive blocks.

BET!
 

tryagain

Newbie level 1
Joined
Jun 14, 2002
Messages
0
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,282
Activity points
797
It is not best ways,this cap will be effected by input voltage and others.
 

Sunrising

Newbie level 6
Joined
May 10, 2004
Messages
14
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
110
tryagain said:
It is not best ways,this cap will be effected by input voltage and others.
Tryagain, would you pls advice what's the best ways?

We use common GND and power supply pins for analog and digital blocks, but the power lines are seperated from pads to various blocks. As for the decoupling capacitors, shall we connect them between the power supply and ground lines for the same block or any power lines is OK?
 

SC3K01

Newbie level 5
Joined
Jan 20, 2003
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
77
When I applied MOSCAP as the on-chip decoupling capacitors, I found that the leakage of those decoupling capacitor is an issue.
The leakages result from subthreshold one and gate tunneling one. Is it a feasible approach to apply reverse-biased junction diodes as the on-chip decoupling capacitors?
 

xinsu

Member level 3
Joined
May 8, 2004
Messages
65
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
379
we had use reverse-biased junction diodes for ESD protection on chip.
 

legend

Junior Member level 1
Joined
Jan 17, 2004
Messages
19
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
165
hi,xinsu,
How to use reverse-biased junction diodes for ESD protection on chip? can you explain it more?

xinsu said:
we had use reverse-biased junction diodes for ESD protection on chip.
 

xinsu

Member level 3
Joined
May 8, 2004
Messages
65
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
379
hi,legend
Add reverse-baised diode arry between different power supply pads,usually connect their grounds.
 

eric1341

Newbie level 3
Joined
Jul 19, 2004
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
28
What value of diode junction capa? How many area is needed for diode junction capa and MOSCAP if use same value of decoupling capa?
 

selvaraja

Full Member level 4
Joined
Jun 1, 2004
Messages
190
Helped
6
Reputation
12
Reaction score
3
Trophy points
1,298
Activity points
1,415
hai ang ,

You can avoid using decoupling capacitor if space a constraint by stacking power rails on top of each other. Yau can alternate power and ground rails like interwinning fingers, that depends on metal availables in your process. This technique builds in decoupling capacistors across the power rails for f.o.c .

rgrds,

selva
 

omsi

Member level 5
Joined
Jan 24, 2006
Messages
93
Helped
7
Reputation
14
Reaction score
4
Trophy points
1,288
Location
London
Activity points
2,105
surround the moscaps byguardring.
make mos caps as big as possible
 

davidwong

Member level 4
Joined
Mar 5, 2006
Messages
76
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,910
SC3K01 said:
When I applied MOSCAP as the on-chip decoupling capacitors, I found that the leakage of those decoupling capacitor is an issue.
The leakages result from subthreshold one and gate tunneling one. Is it a feasible approach to apply reverse-biased junction diodes as the on-chip decoupling capacitors?
Hi SC3K01,

I would like to know how much is the leakage?
by the simulation the leakage of the MOSCAP is 1e-18 range.
Note : I use 0.5um CMOS process
 

l.sant

Newbie level 4
Joined
Apr 18, 2006
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,310
As leakage is your concern I suppose you're using "thin-oxide" devices in a recent technology (130nm or less).. I would not recommend the use of those devices not only because of leakage but also to avoid any robustness and high volume yield issues cause by defects in the oxide or ESD zaps.. In older technologies I've never had a problem using MOS devices as decoupling caps..

Ciao,

LucaS.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top