# MOS as a limiter

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#### parth22

##### Member level 4
HI all,
I have a circuit and I am using here a nMOS as a current limiter. (in the attach image one can see)
when i am doing simulaion, i am getting constant voltage at C=1500uf. why am i not charging the capacitor?
My calculation reference is http://www.bonavolta.ch/hobby/files/MotorolaAN1542.pdf. Page no 8 figure 3.

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• 2022-04-07_15h13_40.png
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Solution
1. when first 5V is there, R6 pulled to gnd and V(B1) = (10K/20K)*VS.......although VS = 42-0.70 = ~41.3V. it means initially V(B1) should be ~21V.
No.
The Q1 base voltage will never drop more than about 0.7V below 42V, since Q1's emitter-base diode immediately starts conducting.
initial VG= 42V and Vs should be
42-0.70V so these are not equal completely. But in simulation if you will zoom in...you will find both voltages are equal (0.003V difference, that is negligibel)
WHY???
What is Vs?
With Q2 on, Q1 is saturated, so it's base and emitter voltages are nearly equal.

why there is a voltage drop across Q1
Because Q1 is regulating the gate voltage to M1 to regulate the current.
the gate-source voltage required...
to make a FET current limiter, you need to sense the current, then feed that to an error amplifier with a reference suitably set..then feed error amplifier output to the gate of the fet in some way.

Its the old trick where the inputs of an opamp with neg feedback are the same.......so make one be from a reference voltage...then the other will magically go to that voltage...ie set the current.

Alternately, you can do a cheap current limiter using an NPN Vbe....use a sense resistor and put it across BE....then make collector pull the gate down....or do it with an PNP, whichever you like.
--- Updated ---

like this but with a fet if you like
--- Updated ---

like this but with a fet if you like
--- Updated ---

here is a LTspice linear current regulator with fet...you can run it in the free LTspice.
Let me know if you want it converted to using hi side pfet

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• Linear current regulator1.zip
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• parth22

Here is what I get for sim - Regards, Dana.

Here is what I get for sim -

View attachment 175307

Regards, Dana.
I don't know where i am doing wrong...can you look into below circuit? Why i am not getting the same simulation results.

#### Attachments

you must pick a mosfet...not just use the default mosfet thing

1.5mf is a very low frequency, not a 1500uF capacitance.

In my sim, simmetrix, mF is mili when applied to a capacitor.

But I will keep this in mind as a check when I do other sims.

Regards, Dana.

Did you set the initial condition of the 1500 uF to 0 volts ?

Regards, Dana.

• parth22

Did you set the initial condition of the 1500 uF to 0 volts ?
No, he didn't.

Problem is lack of understanding of SPICE initial transient solution. You have ideal capacitor (no leakage current) with real transistor (some nA of leakage current). Initial transient solution gives infinite time for calculation of bias point, all capacitance and inductance values zeroed. Simple fix is to set uic option (skip initial operation point solution).

• Easy peasy and parth22

Did you set the initial condition of the 1500 uF to 0 volts ?

Regards, Dana.
Yes thanks I got it.
--- Updated ---

No, he didn't.

Problem is lack of understanding of SPICE initial transient solution. You have ideal capacitor (no leakage current) with real transistor (some nA of leakage current). Initial transient solution gives infinite time for calculation of bias point, all capacitance and inductance values zeroed. Simple fix is to set uic option (skip initial operation point solution).
Thanks.

Here's a simulation using a PNP transistor controlling a P-MOSFET to provide a constant-current charge.
The constant-current limit is approximately 0.65V / R1.
(Note the uic transient simulation option, which starts everything at 0V). --- Updated ---

1.5mf is a very low frequency, not a 1500uF capacitance.
In spice talk, 1.5mf is indeed a 1500µF capacitor.

Here's a revised circuit.
I forgot to protect the gate against the high Vgs voltage from the 42V input, so here its limited to about 10V by the addition of R2.

I could also then use a lower voltage PNP transistor, which has a current limit Vbe threshold of about 0.6V for R1. Maybe a diode from V1 to output to rapidly discharge C1 when power turned off ?

If thats of concern.

Regards, Dana.

Here's a revised circuit.
I forgot to protect the gate against the high Vgs voltage from the 42V input, so here its limited to about 10V by the addition of R2.

I could also then use a lower voltage PNP transistor, which has a current limit Vbe threshold of about 0.6V for R1.

View attachment 175326
What's the logic of your component selection...any theoretical calculation?
--- Updated ---

Here's a revised circuit.
I forgot to protect the gate against the high Vgs voltage from the 42V input, so here its limited to about 10V by the addition of R2.

I could also then use a lower voltage PNP transistor, which has a current limit Vbe threshold of about 0.6V for R1.

View attachment 175326
And also how you will you turn off the PMOS.....(Requirement : 42V will always be on the bus line so one can't turn off the main supply..) so other way?

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What's the logic of your component selection...any theoretical calculation?
Not sure what you want, as it's a pretty simple circuit.
R1 is calculated for the current limit you need.
R2 and R3 were calculated to keep the MOSFET Vgs below its maximum rating.
how you will you turn off the PMOS.....(Requirement : 42V will always be on the bus line so one can't turn off the main supply..) so other way?
Why do you need it turned off?
What signal will you use for turn off?

Below is the circuit with an added transistor the will turn the output off from a 5V signal (high is off). --- Updated ---

Below is the simulation modified to show that the OFF signal can also stop the capacitor charge any any arbitrary time. Last edited:

Not sure what you want, as it's a pretty simple circuit.
R1 is calculated for the current limit you need.
R2 and R3 were calculated to keep the MOSFET Vgs below its maximum rating.

Why do you need it turned off?
What signal will you use for turn off?

Below is the circuit with an added transistor the will turn the output off from a 5V signal (high is off).

View attachment 175333
--- Updated ---

Below is the simulation modified to show that the OFF signal can also stop the capacitor charge any any arbitrary time.

View attachment 175334
Well, I am using a precharge path...so that's why it should be turned off after a certain time. (<200ms, in this time cap 1.5mf will be charged and a constant <1A current can flow.
Yes, it will be controlled from UC signal either 3.3 or 5V. As you add an NPN low side switch.
BTW I would like to explain from my side...please correct me if I am wrong somewhere for the circuit operation.
So initially when 5V is there, Q2 is on, that will turn on the Q1 as well (as base of Q1 will be less compared to Emitter of Q1), that time emitter voltage of Q1 will appear at the GATE of M1. Now to turn on M1, VG should be less VB(less than Vth of M1)...
Is it right way?

Well, I am using a precharge path...so that's why it should be turned off after a certain time. (<200ms, in this time cap 1.5mf will be charged and a constant <1A current can flow.
Only if there's another path for the current besides the capacitor.
Is it right way?
Yes, that explanation sounds correct.

Only if there's another path for the current besides the capacitor.

Yes, that explanation sounds correct.
Yes..this capacitor is an input filter of invertor. so can give constant current further.
Only if there's another path for the current besides the capacitor.

Yes, that explanation sounds correct.
Please take reference of below image...!
Well i would like to draw your attention again. I analysis it again in deep. I have found some issues or questions?
1. when first 5V is there, R6 pulled to gnd and V(B1) = (10K/20K)*VS.......although VS = 42-0.70 = ~41.3V. it means initially V(B1) should be ~21V. But in the simulation it's not.........So am i wrong or am i not looking any aspects.

well overall V(B1) is less than V(E1) so Q1 is on,,,,V(E1) will appear at V(G). so initial VG= 42V and Vs should be
42-0.70V so these are not equal completely. But in simulation if you will zoom in...you will find both voltages are equal (0.003V difference, that is negligibel)
WHY???
And if VGS is alsmot is 0,,,,M1 should not be conduct...and it is not conducting....that's true. I agree.

Now when pulse goes to 0, Q2 is off, V(B1) = VS.....in this case also,,,V(B1) is 0.65 V less than of V(E1),,,,it means Q1 should be conductive....but it is not...Because voltage drop across V(C1E1) is ~3.7V and so VG = ~36V and M1 is conducitve.....
question is why there is a voltage drop across Q1...?

sorry this is little bit long explanation,,,but i am curious now to know excact thing...! #### Attachments

1. when first 5V is there, R6 pulled to gnd and V(B1) = (10K/20K)*VS.......although VS = 42-0.70 = ~41.3V. it means initially V(B1) should be ~21V.
No.
The Q1 base voltage will never drop more than about 0.7V below 42V, since Q1's emitter-base diode immediately starts conducting.
initial VG= 42V and Vs should be
42-0.70V so these are not equal completely. But in simulation if you will zoom in...you will find both voltages are equal (0.003V difference, that is negligibel)
WHY???
What is Vs?
With Q2 on, Q1 is saturated, so it's base and emitter voltages are nearly equal.

why there is a voltage drop across Q1
Because Q1 is regulating the gate voltage to M1 to regulate the current.
the gate-source voltage required for an M1 current of 1A is about -3.7V.

How else could it regulate the current?

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