Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

More than 4.5" length trace without bending

Status
Not open for further replies.

raj_pcbtech

Member level 3
Joined
Aug 9, 2007
Messages
61
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
India
Activity points
1,617
Hi All,

I had routed a mother board which has more than 4.5" length straight trace on the board. There is no possibility to bend the trace. But I studied in some article that more than 3" straight trace will make capacitive effect on the board. Could anyone explain me about this effect? Any help would be greatly appreciated.

Raj
 

A capacitor is consists of two conductors separated by a dielectric - that's the basic definition of a capacitor.

A trace on a PCB is a conductor; the material of the board is a dielectric. Any other trace or plane on the board that is in close proximity to a trace then becomes the second conductor, and the trace then has measurable capacitance.

All PCB traces have self-inductance, and mutual inductance with other traces or structures on the board. All PCB traces have some capacitance - the amount depends on the total area (length x width) of the trace, and the area and proximity of adjacent traces or planes.

There is nothing magic about three inches, or any other arbitrary length. The capacitance of a trace depends on what else is on your board, and how close it is to your trace.

A PCB trace is only one-half of the overall signal path. Every signal must have a return side - that forms a complete signal loop. The larger the loop is (the further away you make the return current flow), the larger the inductance of your trace will be. An ideal board has a return path directly below each signal trace. Normally this is done with a plane layer (either ground or power). As soon as you place that return path, you have increased the capacitance of the trace - BUT, at the same time you have drastically reduced the inductance of the trace by decreasing the signal loop size. Like everything in engineering, there are tradeoffs when designing a printed circuit board.

By controlling the width of the trace, and the distance between the trace and its return path, you can control the impedance of the trace for a given PCB dielectric material. The length of the trace only becomes important when you have signal timing issues that need to be controlled.
 

more than 3" straight trace will make capacitive effect on the board.

Yes, It does!

The longer the line the greater the capacitance.
Capacitance =W*L*Edi/Tdi

Where
W width of the wire
L length of wire
Tdi thickness of dielectric layer
edi permittivity

Moreover,
It was found that the delay of a wire is a quadratic function of its length. This means doubling the length of the wire quadruples its delay. However, RC delays should be considered by the designer only if rise (fall) time at the input is smaller than RC, the rise (fall) time at the line.

In other words, they should be considered only when
TRISE < RC

& now ... solution to your problem...

u can scale it by using a repeater...which can be an inverter to cut the wire into two ;)
 

Any trace on the board must be treated as transmission line. Even when it is not an RF application, underlying physics stays the same. The true is that such transmission lines will MULTIPLAY the input reactance and at the output one can see much different reactance! Let’s see one simple example. Just imagine that you have a VCO that operates on roughly 500 MHz and varactor is connected to the tank with about 5 mm long traces for each of varactor’s pins. The actual varactor’s capacitance is about 7.5 pF according to its datasheet and to the measurements. What the tank will see in such case? The answer is 19.5 pF! This 5 mm per trace length multiplies capacitive reactance and makes actual capacitance much bigger than designer was expected. If we will make these traces longer they will became more and more capacitive and then suddenly switch to inductive reactance! All these processes can be easily seen on Smith Chart as we will go clockwise from any starting point (in the case of discussed example we need to start from the lower capacitive half of the Smith Chart).

When you have a broadband signal the picture is more complicated because now resulting output reactance became frequency dependent. Bending the trace is a different issue. When it is done correctly it is usually have no effect on board performance. It may be easily simulated with any RF simulators. I usually use MicroLINC2 which is very inexpensive, but powerful RF simulation program from appliedmicrowave.com

Best regards,
RF-OM
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top