dineshvv
Newbie level 4
Monte carlo analysis for dynamic logic circuits to estimate leakage pwr and delay?
Is it possible to evaluate leakage power and delay in orcad pspice or capture tool. I need to use 45nm technology or less dan dat. how much pspice will support(technology scale). Another difficulty is am using dual threshold technique for domino logic. Shall i differentiate low vt and high vt device by creating any new model mosfets. Give me an idea or which model transistor is useful in low power design. How to set parameters in monte carlo analysis to estimate the former i said b4.
Is it possible to evaluate leakage power and delay in orcad pspice or capture tool. I need to use 45nm technology or less dan dat. how much pspice will support(technology scale). Another difficulty is am using dual threshold technique for domino logic. Shall i differentiate low vt and high vt device by creating any new model mosfets. Give me an idea or which model transistor is useful in low power design. How to set parameters in monte carlo analysis to estimate the former i said b4.