Monostable Multivibrator help

[anhnha]

Hi all,

I feel very confused with the oppsitition between the explaination in text and the diagram which is illustrated.
The explaination in text:
"When a positive trigger pulse is applied to the input at time t0, the output of the first NOR gate U1 goes LOW taking with it the left hand plate of capacitor CT thereby discharging the capacitor. As both plates of the capacitor are now at logic level "0", so too is the input to the second NOR gate, U2 resulting in an output equal to logic level "1". This then represents the circuits second state, the "Unstable State" with an output voltage equal to +Vcc"

But in the diagram, the capacitor is charging.
As for me, I think that positive trigger pulse is applied to the input at time t0 the capacitor is charged because the output of NOR gate U1 is low and the right plate of cap is High.
But I dont see how cap is discharged because when output of NOR gate U1 is High and the right plate of cap is High, hence there is no voltage dropping in capacitor and cap is not discharged.
Am I right?
Thanks so much.

 

[moottii]

Hi,
first imagine that there is no input pulse.Ok...the output of the first gate is High and also the input of the second gate is High.So the capacitor is fully charged
now imagine a positive pulse is applied to the input.we expect the output of the first gate to be Low.So the left plate became low.we also expect the right plate to be low (because the voltage of cap. can not change suddenly).so the cap. has discharged through the output of first gate (because it is low impedance).now the output of the second gate becomes High.
cap. begins to charge through Vcc until a specific voltage.then output of the second gate becomes Low again.That's it.

 

[erikl]

... when output of NOR gate U1 is High and the right plate of cap is High, hence there is no voltage dropping in capacitor ...

Right, both cap plates' potential is High, i.e. the voltage between both cap plates is (≈) zero. After t₀, the output of U1 with the left plate of C_T goes Low. C_T keeps its difference_voltage=0 , hence the right plate of C_T (V1) also goes Low, s. your timing diagram above.

 

[anhnha]

Thanks so much.
@moottii :

first imagine that there is no input pulse.Ok...the output of the first gate is High and also the input of the second gate is High.So the capacitor is fully charged

Could you explain why the capacitor is charged.
I think that the capacitor is charged only when a positive pulse is applied to the input.

we also expect the right plate to be low (because the voltage of cap. can not change suddenly)

Could you give me a more detailed explaination about this? I think the right plate have to at high level because it is connected to Vcc.
Thanks.

---------- Post added at 21:44 ---------- Previous post was at 21:40 ----------

---------- Post added at 21:46 ---------- Previous post was at 21:44 ----------

Thank a lot.
@erikl :

After t0, the output of U1 with the left plate of CT goes Low. CT keeps its difference_voltage=0 , hence the right plate of CT (V1) also goes Low

Could you give me a more detailed explaination about this? Why the right plate have to go low?
I thought it is high because it is connected to Vcc.
Am I right?
Thanks.

 

[moottii]

why not...
when a positive trigger pulse is applied to the input , on the inputs of the first gate (nor) is High and as you know if one of the inputs of a nor gate was high,the output will be definitely low (look at the truth table of the nor gate).So the left plate of cap. is low.
the other plate will jump exactly from high voltage to low (as I said befor,the voltage of cap. can not change suddenly i=c*dv/dt )
you see...both plates are low
so the cap. is discharged