Then don't cross post to multiple sites or on this site.
Cross posting is an inherently rude and selfish act that has no place on any forum, if you must cross post in the very first post you should always inform others where those cross posts are located so that users can either ignore your post (figuring the question will get answered on the other site) or so they don't repeat something someone already answered, wasting their time trying to help you.
If you run into this timescale issue again just add the -timescale #ns/#ps or whatever you want for the timeunit/timeprecision to the vsim or xvsim or whatever simulator you are using. Doing this will force a default and you won't have to add the directive in all the files.
I run into this issue all the time due to vendor cores having a `timescale in all their (synthesizable) files. Sometimes this is because all the files have #delays on all the assignments. I suspect many vendors use inexperienced people (new grads) to generate their simulation library models, which is a huge mistake. Ran across this issue with a Xilinx DDR model that didn't work correctly unless you put #delays in your RTL to fix the model's race condition problems. The previous model was written by someone who must have written ASIC models before. The "new" improved model was garbage with #1 delays all over the place on the clock input to detect clock edges and on the data to try and compensate for the introduced clock delays. What really surprised me was I complained to the FAE and they told the factory which kept that model for many base version numbers of the tools before it was finally rewritten by someone who obviously knows how to write a simulation model.