module instantiation in verilog

[sun_ray]

Let a module A have one 4 bit input named sigZ. It is needed to instansiate this module A and it is also needed that in the instantiation of A, the four different bits of sigZ will be connected to different four other signals named sig1, sig2, sig3, sig4 from four other different blocks. How can this connection in the instantiation of A, without using concatenation operator?

 

[ivb1991]

Why you don't like concatenation? It's a standard practice to use this operator in such cases.

 

[imbichie]

wire [3:0] sigZ_wire;
assign sigZ_wire[0] =  sig1;
assign sigZ_wire[1] =  sig2;
assign sigZ_wire[2] =  sig3;
assign sigZ_wire[3] =  sig4;

module_A module_A
(
....
  .sigZ   (sigZ_wire),
....
);

If you are not using the concatenation operator, then it will be somewhat like this.

 

[sun_ray]

wire [3:0] sigZ_wire;
assign sigZ_wire[0] =  sig1;
assign sigZ_wire[1] =  sig2;
assign sigZ_wire[2] =  sig3;
assign sigZ_wire[3] =  sig4;

module_A module_A
(
....
  .sigZ   (sigZ_wire),
....
);

If you are not using the concatenation operator, then it will be somewhat like this.

Is this assigning for each bit as shown below not allowed?

A ins_A (.sigZ[0] (sig1), sigZ[1] (sig2), sigz[2] (sig3),............)

 

[imbichie]

A ins_A (.sigZ[0] (sig1), sigZ[1] (sig2), sigz[2] (sig3),............)

As far as I know, it is not allowed in verilog.
Please correct me if I am wrong.