Modular 8 bit Ripple Carry Adder (Help!)- Verilog

[tweaktronics]

I am trying to build a ripple carry adder using a hierarchical verilog structure description. What I have is not working right... out puts are all messed up. My logic is messed up somewhere but not sure where. I grabbed the test bench from a 8 bit multiplier to use for the RCA and so I know I am overlooking something basic... any help would be great. The test bench compares the structural design to a known good behavioral code. but I get errors because they dont match.

here is my code....

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//1-bit full adder
module RCASlice (CO, S, A, B, CI);
 
input A, B, CI;
output S, CO;
wire X1;
wire P1, P2, P3;
 
xor #(2,2)
    U1a (X1, A, CI),
    U1b (S , X1, B);
    
and #(2,2)
    U2a (P1, A, B),
    U2b (P2, A, CI),
    U2c (P3, B, CI);
    
or #(2,2)
    U3a (CO, P1, P2, P3);
    
endmodule
 
//Ripple Carry Adder of 8 bits
module RCAnBITS (CO,S,X,Y,CI);
parameter nBITS = 8;
input [nBITS-1:0] X,Y;
input CI;
output [nBITS-1:0] S;
output CO;
 
wire [nBITS:0] C; //output requires 9bits: C[8] is MSB
genvar i;
 
generate
    assign C[0] = CI;
    assign CO = C[nBITS];
    for (i=0; i<nBITS; i=i+1)
    begin:RCA
        RCASlice m(C[i+1],S[i],X[i],Y[i],C[i]);
        end
    endgenerate
    endmodule

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and my test bench....

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//
// Testbench for 8-bit Ripple Carry Adder
//
 
 
module GoldenDevice(s, x, y);
parameter NBITS = 8;
input [NBITS-1:0] x,y;
output [NBITS:0] s;
 
assign s = x + y;
endmodule
 
 
 
 
module Adder8BitTest;
integer FirstInput, SecondInput;
parameter NBITS = 8;
reg [NBITS-1:0] x, y;
 
// response from Golden device
wire [NBITS:0] sum; 
 
// response from DUT
wire [NBITS:0] s;
 
reg Error;
 
task ReportError;
begin
$display("*** Error: x = %2h, y = %2h, observed p = %4h, expected p =%4h\n",x,y,s,sum);
end
endtask
 
 
//8 bit Ripple Carry Adder
RCAnBITS t1(CO,S,X,Y,CI);
GoldenDevice #(.NBITS(8)) GD(sum, x, y);
 
 
initial
begin
Error = 0;
 
 
 
for (FirstInput = 0; FirstInput < (1 << NBITS); FirstInput = FirstInput+1)       // iterate over all values
    begin
    x = FirstInput;
    for (SecondInput = 0; SecondInput< (1 << NBITS); SecondInput = SecondInput+1)        // iterate over all values
        begin
        y = SecondInput;
        #1000
        if (sum !== s)
            begin
            ReportError;
            Error = 1;
            end
        end
    end
 
if (!Error)
    $display("*** Congratulations!   No errors detected\n");
else
    $display("*** Sorry.    Try again.\n");
    
$finish();
end
endmodule

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- - - Updated - - -

UPDATE: I did find that I forgot to change out the p to an s on the "observed" and "expected" part.... still errors though.

heres a sample of what I get...

*** Error: x = 00, y = 00, observed p =  zzz, expected p = 000

*** Error: x = 00, y = 01, observed p =  zzz, expected p = 001

*** Error: x = 00, y = 02, observed p =  zzz, expected p = 002

*** Error: x = 00, y = 03, observed p =  zzz, expected p = 003

*** Error: x = 00, y = 04, observed p =  zzz, expected p = 004

*** Error: x = 00, y = 05, observed p =  zzz, expected p = 005

*** Error: x = 00, y = 06, observed p =  zzz, expected p = 006

*** Error: x = 00, y = 07, observed p =  zzz, expected p = 007

*** Error: x = 00, y = 08, observed p =  zzz, expected p = 008

*** Error: x = 00, y = 09, observed p =  zzz, expected p = 009

*** Error: x = 00, y = 0a, observed p =  zzz, expected p = 00a

*** Error: x = 00, y = 0b, observed p =  zzz, expected p = 00b

*** Error: x = 00, y = 0c, observed p =  zzz, expected p = 00c

*** Error: x = 00, y = 0d, observed p =  zzz, expected p = 00d

*** Error: x = 00, y = 0e, observed p =  zzz, expected p = 00e

*** Error: x = 00, y = 0f, observed p =  zzz, expected p = 00f

*** Error: x = 00, y = 10, observed p =  zzz, expected p = 010

*** Error: x = 00, y = 11, observed p =  zzz, expected p = 011

*** Error: x = 00, y = 12, observed p =  zzz, expected p = 012

*** Error: x = 00, y = 13, observed p =  zzz, expected p = 013

Not sure whats going on... but the observed is the same for all of it... where'd I screw up?

 

[clpton62]

I'm having the same issue. Also stuck in the RCA testbench due to the errors it encountered and because verilogger can't verify all the possible addend/augend combinations. I hope someone can read this and give an answer because wednesday's TA advice was not helpful at all.

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I think the CI needs to be included in the golden model's equation: {CO,S} = A+B+CI.
The teacher wrote that so I assume it's correct.
Oh and when comparing the sums of first and second inputs you also need to compare the carry outs with a statement like
if (GS !== RCS || GC !== RCC)

But again that's all I got!!