Modifying VEC file, after VCD to VEC file conversion

[nanavaras6284]

Can anyone provide any details regarding what are the modifications required to be done on the vector file generated from VCD file using vcd2vec utility in Synopsys Nanosim.

And what is the syntax for the *.sig file, if I need to limit the input and output signals in the vector file, so that all the signals in the vcd file are not translated to the vectors (like for intermediate wires in the verilog netlist).

regards,
Saravanan

 

[tosonal.jain]

If you want to convert a vcd file to a vec file you can use finesim simulator's fscript utility.

For this you will require to generate a fscrpt command file
Following is an example of the same

1. Run the verilog vector and generate the VCD dump file.
2. Make a fscript command file.
The following is the sample script for the same.

load vcd quads.vcd
open quad.vec
fset vih 0.9
fset vil 0.1
fset slope 1 ns
vinit
vsignal tclksatpml in bin
vsignal txrpll in bin
vsignal trxdata1* out bin
vsignal txtbias* both bin
vrun
4. run command is
fscript <fscript command file name>
5. run command exit

Note: Points to be noted in the above script:
a) The use of wild card(*) is done in the signals where there are the data bus.