Modesim simulation problem

[fsmith]

Hi,

I compiled the following VHDL code in Modelsim and it compiles okay, but when I run a simulation, the output u remains undefined. Can someone please tell me what I am doing wrong.

library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.stdmr_package.ALL;
use work.seu.ALL;


entity b02_dmr is
port (
err0 : in std_logic ;
err1 : in std_logic ;
err2 : in std_logic ;
err3 : in std_logic ;
err4 : in std_logic ;
err5 : in std_logic ;
err6 : in std_logic ;
err7 : in std_logic ;
err8 : in std_logic ;
err9 : in std_logic ;
err10 : in std_logic ;
err11 : in std_logic ;
err12 : in std_logic ;
err13 : in std_logic ;
err14 : in std_logic ;
err15 : in std_logic ;
err16 : in std_logic ;
err17 : in std_logic ;
err18 : in std_logic ;
err19 : in std_logic ;
err20 : in std_logic ;
err21 : in std_logic ;
err22 : in std_logic ;
err23 : in std_logic ;
err24 : in std_logic ;
err25 : in std_logic ;
err26 : in std_logic ;
err27 : in std_logic ;
err28 : in std_logic ;
reset : in std_logic ;
clock : in std_logic ;
linea : in std_logic ;
u : out std_logic );
end b02_dmr ;

architecture test of b02_dmr is

signal stato_0 , stato_1 , n92 , u54 , n93 , n94 , n95 , stato48_2
, n96 , n97 , stato48_0 , stato_2 , n98 , n99 , n100 , n101 , stato48_1
, n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 : std_logic ;

signal stato_0_0 ,stato_1_0 ,n92_0 ,u54_0 ,n93_0 ,n94_0 ,n95_0 ,stato48_2_0
,n96_0 ,n97_0 ,stato48_0_0 ,stato_2_0 ,n98_0 ,n99_0 ,n100_0
,n101_0 ,stato48_1_0 ,n102_0 ,n103_0 ,linea_0 ,n104_0 ,n105_0
,n106_0 ,n107_0 ,n108_0 ,n109_0 ,enable_0 ,clock_0 ,u_0
,seu_0
,seu_1 ,seu_2 ,seu_3 ,seu_4 ,seu_5 ,seu_6 ,seu_7
,seu_8 ,seu_9 ,seu_10 ,seu_11 ,seu_12 ,seu_13 ,seu_14
,seu_15 ,seu_16 ,seu_17 ,seu_18 ,seu_19 ,seu_20 ,seu_21
,seu_22 ,seu_23 ,seu_24 ,seu_25 ,seu_26 ,seu_27 ,seu_28
,seu_29 ,seu_30 ,seu_31 ,seu_32 ,seu_33 ,seu_34 ,seu_35
,seu_36 ,seu_37 ,seu_38 ,seu_39 ,seu_40 ,seu_41 ,seu_42
,seu_43 ,seu_44 ,seu_45 ,seu_46 ,seu_47 ,seu_48 ,seu_49
,seu_50 ,seu_51 ,seu_52 ,seu_53 ,seu_54 ,seu_55 ,seu_56
,seu_57 , enable : std_logic;

begin

linea_0 <= linea ;
stato_0_0 <= resolve_std_logic( seu_0 , err0 );
stato_1_0 <= resolve_std_logic( seu_1 , err1 );
n92_0 <= resolve_std_logic( seu_2 , err2 );
u54_0 <= resolve_std_logic( seu_3 , err3 );
n93_0 <= resolve_std_logic( seu_4 , err4 );
n94_0 <= resolve_std_logic( seu_5 , err5 );
n95_0 <= resolve_std_logic( seu_6 , err6 );
stato48_2_0 <= resolve_std_logic( seu_7 , err7 );
n96_0 <= resolve_std_logic( seu_8 , err8 );
n97_0 <= resolve_std_logic( seu_9 , err9 );
stato48_0_0 <= resolve_std_logic( seu_10 , err10 );
stato_2_0 <= resolve_std_logic( seu_11 , err11 );
n98_0 <= resolve_std_logic( seu_12 , err12 );
n99_0 <= resolve_std_logic( seu_13 , err13 );
n100_0 <= resolve_std_logic( seu_14 , err14 );
n101_0 <= resolve_std_logic( seu_15 , err15 );
stato48_1_0 <= resolve_std_logic( seu_16 , err16 );
n102_0 <= resolve_std_logic( seu_17 , err17 );
n103_0 <= resolve_std_logic( seu_18 , err18 );
n104_0 <= resolve_std_logic( seu_20 , err20 );
n105_0 <= resolve_std_logic( seu_21 , err21 );
n106_0 <= resolve_std_logic( seu_22 , err22 );
n107_0 <= resolve_std_logic( seu_23 , err23 );
n108_0 <= resolve_std_logic( seu_24 , err24 );
n109_0 <= resolve_std_logic( seu_25 , err25 );
U31_0 : stdmr_nor3 port map( stato_0_0, stato_1_0, n92_0, seu_3 );
U32_0 : stdmr_nand3 port map( n93_0, n94_0, n95_0, seu_7 );
U33_0 : stdmr_nand2 port map( n96_0, n97_0, seu_10 );
U34_0 : stdmr_inv port map( stato_2_0, seu_2 );
U35_0 : stdmr_inv port map( stato_0_0, seu_12 );
U36_0 : stdmr_inv port map( stato_1_0, seu_13 );
U37_0 : stdmr_nand2 port map( n100_0, n101_0, seu_16 );
U38_0 : stdmr_or2 port map( n99_0, n98_0, seu_5 );
U39_0 : stdmr_or2 port map( n99_0, stato_2_0, seu_17 );
U40_0 : stdmr_nand2 port map( n98_0, n102_0, seu_18 );
U41_0 : stdmr_or2 port map( n99_0, linea_0, seu_20 );
U42_0 : stdmr_nand2 port map( n98_0, n104_0, seu_21 );
U43_0 : stdmr_nand2 port map( stato_2_0, n105_0, seu_4 );
U44_0 : stdmr_nand2 port map( linea_0, n103_0, seu_6 );
U45_0 : stdmr_or2 port map( linea_0, stato_1_0, seu_22 );
U46_0 : stdmr_nand2 port map( n92_0, n106_0, seu_23 );
U47_0 : stdmr_nand2 port map( linea_0, n92_0, seu_24 );
U48_0 : stdmr_nand2 port map( stato_0_0, n108_0, seu_25 );
U49_0 : stdmr_or3 port map( linea_0, stato_0_0, stato_2_0, seu_9 );
U50_0 : stdmr_nand2 port map( n109_0, n99_0, seu_8 );
U51_0 : stdmr_nand2 port map( stato_0_0, n107_0, seu_15 );
U52_0 : stdmr_or3 port map( n99_0, stato_2_0, stato_0_0, seu_14 );
stato_reg_2_0 : dmr_D_FF port map( enable, clock, stato48_2_0, seu_11 );
stato_reg_1_0 : dmr_D_FF port map( enable, clock, stato48_1_0, seu_1 );
stato_reg_0_0 : dmr_D_FF port map( enable, clock, stato48_0_0, seu_0 );
u_reg_0 : dmr_D_FF port map( enable, clock, u54_0, u );

end test;

 

[ljxpjpjljx]

do you have added the lib to link libriary?

 

[fsmith]

Hi,

Yes, I added stdmr_package and seu to the library work. In fact, I also added all the components in the stdmr_package to the library work.

 

[devas]

Hi,

What is the value of seu_3? This signal has no assignment in the code above, but the resolved signal of seu_3 and err_3 (U54_0) will be clocked and is the output signal u, so when seu_3 has no value assigned, it gets the default value 'U'.
The value 'U' resolves always to 'U', so in that case it is correct that the output signal u has the value 'U'.

Devas

 

[fsmith]

Hi,

seu_3 is the output of gate U31_0 [ U31_0 : stdmr_nor3 port map( stato_0_0, stato_1_0, n92_0, seu_3 ); ]. So thats where it gets its value from.

This code compiles and is simulated without problem in Quartus II simulator.

 

[devas]

Hi,

Oke, I missed that with my Find.

Do you get any (unbound) messages in Modelsim when you start the simulation?

As I do not have the code of your packages I can not try it out what is going wrong in Modelsim.

Devas

 

[fsmith]

hi,

I can email the code to you. what is your email address.

fsmth.

 

[devas]

Hi,

I have send an email to you with my email address.

Devas