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Modelsim V5.7d has been released

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visualart

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modelsim examine

need license.
please
 

leonqin

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modelsim v5.7

who try it with old 5.7c license ?
 

qlyus

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vcd all levels in modelsim

5.7c license works for d.
 

z81203

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modelsim line coverage

so fast, any new feature?
 

qlyus

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modelsim transcript file

It seems mainly for bug fix.


Release Notes For ModelSim SE/PE 5.7d

Copyright Model Technology, a Mentor Graphics
Corporation company, 2003 - All rights reserved.



May 15 2003
______________________________________________________________________

Product Installation and Licensing Information
For brief instructions about product installation please visit the
"install_notes" file on the Model Technology web site. The
install_notes file can be viewed at:
[1]http://www.model.com/products/release.asp
For detailed information about product installation, supported
platforms, and licensing, see the ModelSim Start Here Guide. The
manual can be downloaded from:
[2]http://www.model.com/support/documentation.asp


How to Get Support
For information on how to obtain technical support visit the support
page at: [3]http://www.model.com/support/default.asp


Release Notes Archives
For release notes of previous versions visit the release notes archive
at: [4]http://www.model.com/support/default.asp
or find them in the installed modeltech tree in <path to modeltech
installation>/docs/rlsnotes
______________________________________________________________________

Index to Release Notes

[5]Key Information

[6]User Interface Defects Repaired in 5.7d

[7]Verilog Defects Repaired in 5.7d

[8]PLI Defects Repaired in 5.7d

[9]VHDL Defects Repaired in 5.7d

[10]FLI Defects Repaired in 5.7d

[11]VITAL Defects Repaired in 5.7d

[12]Mixed Language Defects Repaired in 5.7d

[13]General Defects Repaired in 5.7d

[14]Mentor Graphics DRs Repaired in 5.7d

[15]Known Defects in 5.7d

[16]Product Changes to 5.7d

[17]New Features Added to 5.7d
______________________________________________________________________

Key Information
* The following platforms will be discontinued as of the ModelSim
5.8 release:
+ Redhat Linux 6.0
+ Redhat Linux 6.1
+ AIX 4.2
* You must recompile or refresh your models if you are moving
forward from 5.7 Betas or 5.6x or earlier release versions. See
"Regenerating your Libraries" in the ModelSim Start Here Guide for
more information on refreshing your models.
* Acrobat reader version 4.0 or greater must be used to read any
.pdf file contained in ModelSim version 5.5c or greater.
* Product changes and new features mentioned here are introduced in
the 5.7d release. If you are migrating to the 5.7d release from
5.6x or earlier releases, please also consult version 5.7x release
notes for product changes and new features introduced during the
5.7 patch releases. The previous version release notes can be
found in your modeltech installation directory at docs/rlsnotes.
* The HP-UX 10.20 platform is no longer supported as of the ModelSim
5.7 release. The hp700 platform executables are built on HP-UX
11.0. Please note that in order for FLI/PLI shared libraries to be
loaded and executed correctly by the hp700 version of vsim, they
must be compiled and linked on HP-UX 11.0.
* Beginning with the 5.6 release (on Windows platforms only),
attempts to link in libvsim.lib or tk83.lib using the Microsoft
Visual C++ linker version 5.0 will fail with a message similar to
"Invalid file or disk full: cannot seek to 0xaa77b00". Microsoft
Visual C++ version 6.0 should be used.
______________________________________________________________________

User Interface Defects Repaired in 5.7d
* User-specified preference geometries that were partial (only
specified size or location) or used offsets with South or East
gravity (i.e. WxH-X-Y) were not handled correctly. These alternate
forms of geometry specification are now supported.
* Added the Verilog 2001 keywords to the Source window keyword
highlighting list.
* If you use two or more Wave windows, the add wave -window < wname>
sig1 command now sets wname as the default Wave window.
* Statement coverage reports did not mark FOR...GENERATE and
IF...GENERATE (VHDL) statements as being executed because these
statements are evaluated at elaboration time. These statements no
longer produce coverage information, and therefore don't appear as
unexecuted in coverage reports.
* Colorization of the transcript took excessive time if a line
starting with # ********** appeared in the transcript. Lines like
this can be generated by VHDL textio or the Verilog $display
system task. The # ** confused the pattern matching code for
assert messages.
______________________________________________________________________

Verilog Defects Repaired in 5.7d
* The Verilog file I/O tasks such as $fdisplay, $fmonitor, etc. did
not check that the file or multichannel descriptors were valid. An
error message is now given for invalid types.
* Removed "none" from the Verilog 2001 reserved word list.
* The simulator crashed when a generated instantiation was accessed
with an out-of-range index.
* vlog incorrectly required a ";" at the end of an attribute list
inside of an attribute statement.
* A continuous assignment having a value of type real on the
right-hand side produced incorrect results. Also, closely related,
a value of type real connected to a module port produced incorrect
results. In both cases the real should have been converted to a
32-bit integer value.
* An SDF RECREM annotation would not annotate a lone RECOVERY or
REMOVAL specify statement in optimized cells.
* On Win32, single-stepping over Verilog file I/O tasks sometimes
resulted in a corrupted file handle.
* vlog crashed with an internal error when compiling a module
instantiation within an 'else' generate statement that connected a
literal value to a module port by name.
* vlog crashed while compiling a combinational UDP with ANSI-style
arguments where the output was declared as a 'reg' (DR 341631).
This now gives an error message rather than crashing.
* Designs with both a parameterized array of instances and a
generate loop crashed during elaboration.
* The `protect directive caused vsim to freeze when a "reg"
declaration was protected for a module port name that was not
protected. The port name is now left unprotected.
* Defparams inside generate-conditional statements did not always
propagate parameter values to lower levels in the design.
* A parameter initialized with a ternary expression having a
constant selector resulted in a compiler crash in some unusual
cases.
* A design compiled with -fast resulted in false "part-select out of
bounds" errors in some rare cases.
* An SDF interconnect delay from an I/O port to an I/O or input port
in some cases resulted in incorrect behavior when using
+multisource_int_delays.
* Verilog cells containing non-blocking assignments and compiled
-fast +nocheckSUDP might not have evaluated correctly.
* A design compiled with -fast resulted in an internal error in some
cases.
* A design compiled with -fast issued false "part-select out of
bounds" error messages in some cases.
______________________________________________________________________

PLI Defects Repaired in 5.7d
* tf_getnextlongtime() returned incorrect times when the time unit
was different from the simulator time precision.
______________________________________________________________________

VHDL Defects Repaired in 5.7d
* A VHDL port of mode out or inout could have incorrectly
initialized drivers if the port did not have an explicit
initialization value and the actual signal connected to the port
had explicit initial values. Depending on a number of factors,
ModelSim could incorrectly use the actual signal's initial value
when initializing lowerlevel drivers. The old pre-5.7d behavior
can be matched by using the compiler switch -nonstddriverinit.
Note that the switch -nonstddriverinit does not cause all
lowerlevel drivers to use the actual signal's initial value; it
only affects the cases in which the older versions used the actual
signal's initial value.
* Certain null array operands of the implicit concatenation operator
resulted in bad code being generated. This caused the simulator to
crash.
* The code coverage feature was not instrumenting VHDL package
bodies. Package body code coverage, however, does not retain
instance-specific information. The statement counts are
incremented in the same single buffer, no matter who calls the
package subprogram. This matches the behavior of the 5.6 version
of code coverage. Standard IEEE packages, accelerated packages and
MTI packages are automatically excluded from coverage. These
packages include: standard, std_logic_1164, textio, numeric_bit,
numeric_std, std_logic_arith, std_logic_signed,
std_logic_unsigned, std_logic_textio, std_logic_misc,
vital_primitives, vital_timing, vital_memory, vl_types, and util.
* Environment variables specified in the filename parameter to the
std_developerskit, std_mempak functions, Mem_Dump, and Mem_Load
were not expanded.
* Merged processes that had drivers created because of subprogram
calls generated bad code if multiple processes drove these
signals. The bad code crashed or created only one driver.
* If a clocked process had a vector signal in the sensitivity list,
in some cases the signal would be dropped from the sensitivity
list. This resulted in incorrect simulation results.
* Objects declared within a VHDL subprogram were not accessible by
the ModelSim examine, find, and change commands if the subprogram
was declared within the scope of a process.
* The step -over command sometimes incorrectly executed a process to
the next wait statement rather than the next statement to be
executed. This occurred only on HP-PA 32-bit platforms.
______________________________________________________________________

FLI Defects Repaired in 5.7d
* mti_GetVarSubelements() was getting a memory allocation failure
when used on null arrays.
* mti_GetParentSignal() could cause the simulator to crash when the
parent of a VHDL signal was an object in a Verilog module.
______________________________________________________________________

VITAL Defects Repaired in 5.7d
* Highestlevel VITAL accelerations should not have been applied to a
level1 architecture in the presence of an inout port.
* Parallel delay paths were not able to be annotated by an SDF file.
______________________________________________________________________

Mixed Language Defects Repaired in 5.7d
* The -v2k_int_delays switch caused Xs to propagate in a design if:
+ a VHDL design unit was instantiated within a Verilog design
unit
+ the VHDL design unit was driven by an input/inout from the
instantiating Verilog design unit
+ the Verilog input/inout was not annotated with an
interconnect delay
______________________________________________________________________

General Defects Repaired in 5.7d
* On x86-based architectures (Windows and Linux), the code generator
could use excessive stack space. If too much stack space was used
the simulator would crash without a traceback. This was most
likely to occur when elaborating a very large netlist.
* Occasionally the report generated by the line coverage option
would contain lines numbered "0". This was a result of an odd
combination of overloaded identifiers (e.g. an enum named FIRST
and a function named "First"), used as case labels.
* The code coverage feature did not differentiate branches for
branch coverage in case statements where multiple choices matched
the same alternative. To get this functionality you must use the
compile time option -coverBranch. This option is the same for vcom
and vlog.
* The -coverage option was not saved in elaboration files so
coverage was not enabled when an elaboration file was loaded.
* Signal Spy did not correctly recognize Verilog vectors of length 1
( ex. reg [0:0] vec_one; ) as vectors.
* In ModelSim 5.7c the run -step command was broken. Using the
command resulted in the message "Unknown option -step". As a
result of this defect the F11 function key did not work.
* vmap did not issue a warning if the -c option was used with the
MODELSIM environment variable or if -c was used and a local
modelsim.ini file already existed. The -quiet option suppresses
these warnings.
* If you received ModelSim error 3274, "Empty built-in function
pointer(#)....", later executions of the vsim command may have
caused the simulator to crash. This problem only existed on
Windows PE, Windows SE, Linux SE, and RS6000 SE versions of
ModelSim.
* $dumpoff in the VCD file did not work correctly.
* Running vsim with the -restore switch on Red Hat 8.0 caused an
out-of-memory error.
* Versions of hp700 ModelSim newer than 5.5f crashed (with a SIGILL)
in vsim. The SIGILL occurred on HP B180 9000/778 computers running
HPUX 11.00.
* Certain VHDL clocked processes crashed in some cases when
optimizations and code coverage were activated.
______________________________________________________________________

Mentor Graphics DRs Repaired in 5.7d
* DR 00106880/SC340057 - "Source Window edits are lost if a design
is loaded".
* DR 00107687/SC340955 - ModelSim would crash when attempting to
drag an item from the Source window to another window. This would
occur when there were optimized VHDL components in the design, and
the dragging was initiated from the toplevel design unit.
* DR 00107748/SC341021 - UM-342 include an additional note about
coverage.
* DR 00107617/SC340875 - Several DSC compliance issues have been
resolved with postscript file generation from the Wave window.
* DR 00107619/SC340877 - Some paper sizes would cause Tcl errors
when printing postscript from the Wave window. The first time
printing postscript with this patch release, be sure to go to the
Page Setup screen and select the correct paper size to make sure
all values are correct.
* DR 00108136/SC341451 - Concatenation of an empty string with
another string causes crash when run.
* DR 00103325/SC336094 - ModelSim is producing errors on valid VHDL.
* DR 00106680/SC339836 - ModelSim crashes with postlayout Xilinx
simulation.
On x86-based architectures (Windows and Linux), the code generator
could use excessive stack space. If too much stack space was used
the simulator crashed without a traceback. This was most likely to
occur when elaborating a very large netlist.
* DR 00106706/SC339864 - Need to be able to clear transcript in
BATCH mode.
The command "transcript file ?filepath?" has been added to query
or set the pathname for the transcript file. When a new file is
specified, the existing transcript file is closed and a new
transcript file opened. If the pathname is set to an empty string
("") the the existing file is closed and no new file is opened.
This command is an alias to the existing command: "set
PrefMain(file)" which has the same behavior.
* DR 00106821/SC339992 - misleading message: (All branch statements
covered).
* DR 00107268/SC340498 - ModelSim rejects valid verilog2001
attribute syntax.
* DR 00122477 - Changes in state of some signals listed in a process
sensitivity list do not cause the process to be activated in 5.7c
but did in 5.6x.
* DR 00105824/SC338893 - Optimized Verilog assignments are missing
the "arrow" in the Source window.
* DR 00107374/SC340616 - $fdisplay is writing to STD_OUT.
* DR 00121803 - Problem with passing parameters in Verilog generate
clause.
* DR 00122267 - Process merging causes ModelSim to crash.
* DR 00108301/SC341631 - Compiler crashes when parsing ANSI C style
ports in user-defined primitive.
______________________________________________________________________

Known Defects in 5.7d
______________________________________________________________________

Product Changes to 5.7d
______________________________________________________________________

New Features Added to 5.7d
* The command "transcript file ?filepath?" has been added to query
or set the pathname for the transcript file. When a new file is
specified, the existing transcript file is closed and a new
transcript file opened. If the pathname is set to an empty string
("") the the existing file is closed and no new file is opened.
This command is an alias to the existing command: "set
PrefMain(file)" which has the same behavior.
* An option has been added to vsim to control the number of Verilog
SDF missing instance messages that will be emitted before
terminating vsim. The option is -sdfmaxerrors n where n is the
maximum number of missing instance error messages to be emitted.
* vcd dumpports is now able to generate unique vcd variable names
for ports even if those ports are connected to the same collapsed
net. The -unique option to vcd dumpports and the +dumpports+unique
option to vsim activate this feature.
* The vlog compiler can now be told to generate a warning whenever
an unknown plus option is encountered. This functionality can be
turned on by setting the variable Show_BadOptionWarning in the
modelsim.ini file. This variable is set to "off" by default.
* An option was added to the coverage reload command to allow
merging of coverage statistics from testbenches of different
names. The option -root <name> changes the name of the root
testbench to the specified name for the file being reloaded.
 

allegro

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vlog option verilog2001

Can modelsim save and continue the next time?It is too long to run all simulation at once,I hope to run all simulation by parts.
 

hoangthanhtung

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modelsim reserved words

allegro said:
Can modelsim save and continue the next time?It is too long to run all simulation at once,I hope to run all simulation by parts.

if you use the evaluation modelsim, Model company limits the size of HDL file about 500 line, so you do not simulink the large design.
And if use the copyright modelsim, it is O.K for you.
Bye
 

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