Dear TrickyDicky and Shnain,
first of thanks a lot for you time to reply my question.
>>"If it is sensitive to clock, and you have followed the synchronous template properly, you dont need to have other signals in the sensitivity list, only the clock (and reset if you want an async reset)."
precisely this is what my understanding is and used topology in the design.
"Why dont you post the code you're having problems with?"
I wish I could but this design contains almost 50+ vhdl files and this malfuntion is observed only when simulating top level. same design simulated in NC Launch (NC sim) works perfectly fine.
I am trying to play around the optimization stuff dne by Modelsim. I will update as soon as I get a fix for it .
Dear Shanin,
"If it is sensitive to clock, and you have followed the synchronous template properly, you dont need to have other signals in the sensitivity list, only the clock (and reset if you want an async reset)."
I found in Modelsim 6.5SE , while doing functional simulation (RTL) code, if any signal is missing in sensitivity list at some stage a malfunction appears in simulation. netlist (after PnR) same design works fine since those process are already converted to edge sensitive FFs.
once again , I am grateful for you kind replies, I will update about it once I reached to a conclusion.
best regards,
Mirzaaur