modelSIM question about VHDL to schematic

[TekUT]

I like to know if there is a way to show a equivalent gate level schematic of a VHDL entry. This is just to make some VHDL pratics by starting from scratch gate schematics, then traslate it in VHDL, compile it, simulate and if there is this possibility also look at the gate level and compare it with the original one...

Tnx
Powermos

 

[karikalan_t79]

gate level, if you target for fpga , you can see technology map of the rtl view otherwise if you go for asic, then target techology in particular synthesis tool