Modelsim problem with signal initialization

[Hugo17]

With Modelsim I would like to test a code but one signal always remains uninitialized. Here a code snipped to explain the problem with Modelsim:

-- Signal Declaration
signal shifter 			: std_logic_vector(0 to 6);
signal led_out_temp 		: std_logic;	


process (reset_reset_n) is
begin
	if reset_reset_n = '0' then
		shifter <= (others => '0');           -- After reset_reset_n goes to '0' shifter is '0000000'
		led_out_temp <= '0';                  -- Always has the value 'U'
	end if;
end process;

When I step through it I can check the values but even after stepping out of the process the signal "led_out_temp" is 'U'. Can someone tell me why?

 

[K-J]

Two potential reasons:
- reset_reset_n never happens to go to '0' in your simulation
- There are multiple drivers of led_out_temp. To find the other one you can either use the 'drivers led_out_temp' command at the Modelsim prompt or change led_out_temp from std_logic to std_ulogic, compile and the compiler will flag the multiple drivers.

Kevin Jennings

 

[ads-ee]

Modelsim reports multiple drivers with an X not U.

 

[TrickyDicky]

Modelsim reports multiple drivers with an X not U.

No it doesnt.
'U' driven with anything results in 'U'

 

[ads-ee]

No it doesnt.
'U' driven with anything results in 'U'

Ran a test case on this and you are absolutely right, I've been using Verilog so much that I didn't realize that VHDL handles this differently. Verilog just makes everything X right off the bat, so there isn't a U (though I've seen U's in some of my simulations before...mixed mode).

Tricky thanks for pointing out my mistake (I can always trust in your knowledge of VHDL). :thumbsup:

 

[TrickyDicky]

Thats because verilog only has 4 states - X 0 1 and Z, defaulting to X. It uses X to cover VHDL's 'U', 'X' and '-' and 'W'