Modelsim Fatal error: "TOO MANY PORT CONNECTONS" Help me!

[raymondxuym]

Hi guys:

I tried to load a testbench in Modelsim after successful compilation in Quartus and Modelsim. But it encountered a fatal error: "** Fatal: (vsim-3365) /home/yumeng/Desktop/proc_testbench.v(33): Too many port connections. Expected 9, found 20."

It seems that the ports of module System are mismatched but I think it works well.

Code of the System module:

/* Altered System module for testbench. */
module System(DIN, Reset, PB, clock, WR_MEM_out, ADDR_out, DOUT_out, DONE, IR_out, R0_out, R1_out, R2_out, R3_out, R4_out, R5_out, R6_out, R7_out, A_out, G_out, CW);
input [15:0]DIN;
input Reset;
input PB;
input clock;
output wire WR_MEM_out;
output wire [15:0]DOUT_out;
output wire [15:0]ADDR_out;
output wire DONE;
output wire [15:0]IR_out;
output wire [15:0]R0_out;
output wire [15:0]R1_out;
output wire [15:0]R2_out;
output wire [15:0]R3_out;
output wire [15:0]R4_out;
output wire [15:0]R5_out;
output wire [15:0]R6_out;
output wire [15:0]R7_out;
output wire [15:0]G_out;
output wire [15:0]A_out;


//Control Wires
output wire [25:0]CW;
wire gnz;
wire [15:0]BusWires;


//Enables
wire R0_en, R1_en, R2_en, R3_en, R4_en, R5_en, R6_en, R7_en, A_en, G_en, IR_en;
wire ADD_SUB, COUNT_en, ADDR_en, DOUT_en, WR_MEM_en;
wire [9:0]Mux_sel;
assign Mux_sel[9:0] = CW[9:0];
assign R0_en = CW[10];
assign R1_en = CW[11];
assign R2_en = CW[12];
assign R3_en = CW[13];
assign R4_en = CW[14];
assign R5_en = CW[15];
assign R6_en = CW[16];
assign R7_en = CW[17];
assign A_en = CW[18];
assign G_en = CW[19];
assign IR_en = CW[20];
assign ADD_SUB = CW[21];
assign COUNT_en = CW[22];
assign ADDR_en = CW[23];
assign DOUT_en = CW[24];
assign WR_MEM_en = CW[25];


//Data not defined in output
wire [15:0]ADD_SUB_out;
wire [7:0]X_REG;
wire [7:0]Y_REG;




//Instantiate Registers
registers R0(Reset, R0_en, clock, BusWires, R0_out);
registers R1(Reset, R1_en, clock, BusWires, R1_out);
registers R2(Reset, R2_en, clock, BusWires, R2_out);
registers R3(Reset, R3_en, clock, BusWires, R3_out);
registers R4(Reset, R4_en, clock, BusWires, R4_out);
registers R5(Reset, R5_en, clock, BusWires, R5_out);
registers R6(Reset, R6_en, clock, BusWires, R6_out);
registers_count R7(Reset, R7_en, COUNT_en, clock, BusWires, R7_out);
registers A(Reset, A_en, clock, BusWires, A_out);
register_g G(Reset, G_en, clock, ADD_SUB_out, G_out, gnz);
registers IR(Reset, IR_en, clock, DIN, IR_out);
registers ADDR(Reset, ADDR_en, clock, BusWires, ADDR_out);
registers DOUT(Reset, DOUT_en, clock, BusWires, DOUT_out);
flip_flop WR_MEM(Reset, clock, WR_MEM_en, WR_MEM_out);


add_sub stuff(A_out, BusWires, ADD_SUB, ADD_SUB_out);
data_mux mux(Mux_sel, R0_out, R1_out, R2_out, R3_out, R4_out, R5_out, R6_out, R7_out, DIN, G_out, BusWires);




three_to_8_decoder x_decoder(IR_out[2:0],X_REG[7:0]);
three_to_8_decoder y_decoder(IR_out[5:3],Y_REG[7:0]);


control M1(IR_out[8:6], X_REG, Y_REG, PB, Reset, clock, gnz, CW[25:0], DONE);


endmodule

Code for part of the testbench:

Code:

`timescale 1 ps / 1 ps
module proc_testbench;


  wire PB; /* Run */
  wire Reset;
  wire enable; /* a generic write enable */
  wire wren;
  wire leden;
  wire done;
  wire clock;
  wire [15:0]mem_out;
  wire [15:0]address;
  wire [15:0]dout;
  wire [8:0]IR;
  wire [15:0]REG0;
  wire [15:0]REG1;
  wire [15:0]REG2;
  wire [15:0]REG3;
  wire [15:0]REG4;
  wire [15:0]REG5;
  wire [15:0]REG6;
  wire [15:0]PC; /* Register 7 */
  wire [15:0]AR;
  wire [15:0]GR;
  wire [15:0]led_out; /* LED output */
  wire [25:0]control;




  assign wren = (~address[15] && ~address[14] && ~address[13] && ~address[12])?(enable):0;
  assign leden = (~address[15] && ~address[14] && ~address[13] && ~address[12])?0:(enable);


  proc_gen StimulusGenerator (PB, Reset, clock);
  System DUV_1 (mem_out, Reset, PB, clock, enable, address, dout, done, IR, REG0, REG1, REG2, REG3, REG4, REG5, REG6, PC, AR, GR, control); // Line 33(Error line)
  irram DUV_2 (address[6:0], clock, dout, wren, mem_out);
  register_LED DUV_3 (Reset, leden, clock, dout, led_out);
  proc_check Checker (mem_out, Reset, PB, enable, wren, leden, done, clock, address, dout, control, done, IR, REG0, REG1, REG2, REG3, REG4, REG5, REG6, PC, AR, GR, led_out);
  
endmodule

I think the 20 port connections are matched properly. Could anyone figure out what is the problem?
Thanks in advance!

Yumeng

 

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Are you sure you are compiling the correct design files in Modelsim? This is the type of error you see when you've been editing a different file than the one getting compiled. It also looks like you have swapped DOUT_out and ADDR_out connections on DUV_1. I would start using named port mapping instead of the error prone and unreadable positional port mapping. Right now you have the following connections...

---

Code Verilog - [expand]
1
2
3
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// ...
  .WR_MEM_out (enable),
  .DOUT_out (address),
  .ADDR_out (dout),
  .DONE (done),
// ...

---

Next time please use syntax tags, code tags are only good for small amounts of code, when I see almost 100 lines of code without syntax tags I sometimes don't even look at the code or even try to help.

Also you should use Verilog 2001 module ports, instead of copying the port names in two places. I haven't run across a tool that doesn't understand at least that part of Verilog 2001.

Why is it that universities keep teaching such antiquated syntax and unreadable coding standards, besides not even teaching them useful basic stuff like how to cross clock domains? No wonder so many interns I've interviewed over the years have failed to make the cut.

Regards