Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ModelSim doesn't continue loading my design

Status
Not open for further replies.

taskmn57

Newbie level 5
Newbie level 5
Joined
Jul 13, 2009
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,372
Hi,

I am simulatin my VHDL code in modelsim through Xilinx ISE there are many cases that when I run simulation modelsim runs and stops at below stage!... I don't see what has caused this problem:

# vsim -lib work -voptargs=\"+acc\" -t 100ps work.SDI_Ftest
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading ieee.numeric_std(body)
# Loading work.sdi_ftest(behavior)#1
# Loading work.sdi_f_detector(behavioral)#1
# Loading work.pattern(behavioral)#1


it never goes on below messages and thus run> will not appear at all.

# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body

run>


I appreciate any help if you have any idea.

Regards,
Hossein Moradi
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top