ModelSim doesn't continue loading my design

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taskmn57

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Hi,

I am simulatin my VHDL code in modelsim through Xilinx ISE there are many cases that when I run simulation modelsim runs and stops at below stage!... I don't see what has caused this problem:

# vsim -lib work -voptargs=\"+acc\" -t 100ps work.SDI_Ftest
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading ieee.numeric_std(body)
# Loading work.sdi_ftest(behavior)#1
# Loading work.sdi_f_detector(behavioral)#1
# Loading work.pattern(behavioral)#1


it never goes on below messages and thus run> will not appear at all.

# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body

run>


I appreciate any help if you have any idea.

Regards,
Hossein Moradi
 

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