Modeling of the continuous time sigma delta modulator

[Alan_yi]

sigma delta matlab

As the title

I will start the modeling work on several topogies of the sigma-delta modulator in order to compare the performance of the single loop, cascaded, lesilie-sign structure.And all of them will be realized in continuous-time domain.
At first, I want to use matlab to set up these models, but it seems that matlab is not suitable for the continuous time SD.Most people use spice to do the job.
Is there any exsiting continous time SD model that could be used as a reference?I am wandering why matlab can't do the job and how to start the continous-time SD modeling work(any good paper on it?).Thx!

 

[gsuarez]

rz nrz sigma delta jitter

Try using Verilog-A, Verilog-AMS or VHDL-AMS. Check this paper:

**broken link removed**

Regards,

George

 

[sixth]

continuous-time+sigma delta+pdf

As the title

I will start the modeling work on several topogies of the sigma-delta modulator in order to compare the performance of the single loop, cascaded, lesilie-sign structure.And all of them will be realized in continuous-time domain.
At first, I want to use matlab to set up these models, but it seems that matlab is not suitable for the continuous time SD.Most people use spice to do the job.
Is there any exsiting continous time SD model that could be used as a reference?I am wandering why matlab can't do the job and how to start the continous-time SD modeling work(any good paper on it?).Thx!

Hi, alan
I don't know why people say matlab is not suitable for modeling of continuous time sigma delta modulators. I have built up a CTSDM using simulink toolbox in matlab and realize it in transistor level, the results are almost identical. So, I think Matlab is a good tool for behavioral simulation.
sixth

 

[Alan_yi]

sigma delta continuous time maple

Thanks george.
Hi, Sixth
I have a dicussion with these people,some of them recommend matlab with maple to do the symbolic caculation.For the simulink design,there is some tool box for discrete time model,and for continuous time model, is it just to replace the Z domain integrator with s domain integrator.

 

[beckchm]

simulink pspice pain

who has the reference about the delta sigma modulators

thanks

 

[vinsdigs]

continuous time sigma delta matlab

hi, Is it possible to share more information about the design methodology for CT sigma delta modulators?

I have seen some people use the impulse invariant transform to convert the DT models of single loop higher order SDM into CT equivalents. However, i realize there are some drawbacks to this approach.

Some researchers have started the design in CT domain but then transformed to DT for simulations to save time. Can all non-idealities be captured and studied well by this method?

Is time the only issue in simulating CT SDM in CT instead of using the transformation?

I appreciate your inputs.

 

[obi1]

continuous time sigma delta toolbox

i`m interested to about sigma-delta mathlab modeling and i search some simulink toolboxes but there are very dificult to find; help !

 

[grobar]

sigma delta modulator dt-to-ct

I've implemented CT SD in matlab, not using simulink cause I wanna see exactly what's happening when you "play" with parameters.
Simulation is really pain in the ass especially when you want to calculate the integrator coefficients !! It takes a looooooooooot of time cause feedback factor has to be updated every time(after each period T):
fbfactor*(heaviside(t-begin_pulse)-heaviside(t-end_pulse)) if you use rectangular DAC pulses ...I'm doing this for 3rd order single loop 1 bit (and 4 bit) CT SD. I'm using square waves and also exp. pulses for DAC for RZ as well as NRZ. Number of samples is 8192=2^13.

I have FB,FF and hybrid toplogies implemented,for RZ and NRZ,square waves and exp. .

I didn't go from DT to CT , to calculate the coefficients cause that's already been done... I've started in CT using matlab symbolic toolbox & using maple commands.
Hybrid topology using exp. pulses has never been published in any papers + I plan to see the effect of jitter ...

Anyway good luck to you, it's a lot of fun but also a lot of blood ,sweat and tears lol...

 

[vinsdigs]

you are doing some cool stuff. i guess its worth the blood and tears I am designing 3rd order 3 bit RTZ and i understand your joys and frustrations. But why dont u simulate in DT. And somehow i never felt exp is a good choice coz although it reduces the jitter senstivity, its not good for LP modulators.

To my understanding, hybrid modulators have the advantage that the switch non idealities are reduced by the gain of the CT blocks before it (so great for LV) and it has more AAF than just DT SDM. Further, since the first integrator consumes the most power, using CT block and NRZ/RZ DAC is better for LP instead of a discrete time block. But it still suffers from jitter noise and substrate coupled noise.

It would be great if we could keep in touch and try to solve our problems as we go but I think its better if we discuss this offline. you could email me at vinsdigs@yahoo.com if you are interested.

Thanks for the posting and Good luck with your research.

 

[grobar]

I have the script in maple and also one in matlab to calculate those coefficients from DT to CT but only for FB and FF. Plus I want 3D graphs , you know, SNR,coeff1,coeff2,coeff3...Going to CT from DT you get "optimal" integrator coeffs but what about SNR? If DT to CT gives me (0.2,0.5,0.8) and 70dB SNR and I need 65 dB for my specs than that's great but how about (0.1,0.4,1) and 69dB ? I get my specs too and as a designer I want to have as much choices as I can get .
Anyway, this is my thesis so it's not really a 4 year research, I don't have a lot of time to check all possibilities :-(. You're right about hybrid toplogy though but as far as LP goes I can't tell you anything about that cause I'm just doing the things I described above but I'm defintiley gonna ask my promotor about the thing you've mentioned exp. not being that good choice for LP !!!

How are you implementing your 3rd order SDM, in MATLAB or ...?

By the way for RZ I'm using pulse_start=0.5*Tper and pulse_end=Tper
For NRZ pulse_start=0.5*Tper and pulse_end=1.5*Tper .

My email is grobarrr at gmail dot com if you need to ask me something in private , but we can continue here maybe others are working on this too and can jump on and join us !

 

[meghna]

Hi,

I need to model a second-order Sigma Delta modulator having multi-bit quantization (using SIMULINK). I have found good articles related to modelling of Op-amp non-idealities and clock jitter. My problem is related to modeling of quantizer and its non-idealities like comparator-hysteresis and offset voltage.
How to model it in Simulink?

I need some help regarding the modelling of DAC non-linearities also. Please suggest me if you have any idea.

Thanks & Regards
Meghna

 

[tsb_nph]

Good starting document for behavioral modeling of continuous time sigma-delta ADC's :
**broken link removed**

 

[chungming]

Matlab simulate SDM it good
Transistor level transcient simulatiom almost the same with matlab result
But be careful transistor level simulation(like spectre or spice) is no adding MOS noise like thermal & flicker noise source.
So you must adding that to reach a practical result.

 

[jiaming_lee]

I've implemented CT SD in matlab, not using simulink cause I wanna see exactly what's happening when you "play" with parameters.
Simulation is really pain in the ass especially when you want to calculate the integrator coefficients !! It takes a looooooooooot of time cause feedback factor has to be updated every time(after each period T):
fbfactor*(heaviside(t-begin_pulse)-heaviside(t-end_pulse)) if you use rectangular DAC pulses ...I'm doing this for 3rd order single loop 1 bit (and 4 bit) CT SD. I'm using square waves and also exp. pulses for DAC for RZ as well as NRZ. Number of samples is 8192=2^13.

I have FB,FF and hybrid toplogies implemented,for RZ and NRZ,square waves and exp. .

I didn't go from DT to CT , to calculate the coefficients cause that's already been done... I've started in CT using matlab symbolic toolbox & using maple commands.
Hybrid topology using exp. pulses has never been published in any papers + I plan to see the effect of jitter ...

Anyway good luck to you, it's a lot of fun but also a lot of blood ,sweat and tears lol...

Hi there:

I have also studied CT delta-sigma recently. I am interested in what you said " not go from DT to CT", which is not like what I have learned from other papers or books. Do you have some particular matlab tool box, and what's your design procedure? Do you have great articls to read and follow?

besides, non-ideality including extra-loop, muti-bit non-linearity, and clock jitter are always problems for the design, would you like to intriduce some, since you have design experience on it. Thank you!!

Best Regards

Jimmy

 

[grobar]

Yeah I know I've read those papers too but sometimes you have to come up with something new p ...

In papers they equal DT loop gain and CT loop gain and use residues theorem or modified z transform to calculate the "optimal" coeffs. They get their DT coeffs using Schreier matlab toolbox and so on.

I sweep my coeffs (matlab sucks when you use nested for loops by the way). I use my knowledge from FF en FB to get a starting point for the coeffs for my hybrid topology. Then I plot SNR vs coeffs 3D plot and see what are the best coeffs not compromising stability of course.

On clock jitter...I start by calculating the amplitude of the exp. pulse equaling the surface of the square waves for [0,Ts] to that of the amp*exp_pulse for [0,Ts]. Then I replace square waves feedback with exp. pulses and look for improvement. Today I'm going to check it out, simulation for hybrid-square waves are done and I have some for exp. pulses. I'm gonna compare them and see what's new (or not p ). I'm talking about 1 bit and RZ, multi bit and NRZ have yet to be simulated but cause simulations take a lot and I mean a lot of time I hope I can get all of this done before my gradutation and the deadline is 22the of may so I'll need some devine intervention to check it it all out ))))))))).

Maybe I'll make a matlab toolbox for simulating the CT we'll see, stay tuned...

 

[grobar]

Just to tell one more thing exp pulses kicked ass when it came to jitter I could easily have 47ps jitter without SNR degradation. I've implemented sine pulses too and they gave also good very results.

For those who wonder which topology was best, it was the hybrid one for a 3rd order single bit single loop I got SNR=65 dB for FF it was 61dB of for feedback 60dB.

When it came to jitter RZ en NRZ weren't good at all, I'm talking about 1 bit case, (in papers you'll find that NRZ and multi bit quantizer are the best choice). Exp and sin pulses kicked ass !

 

[beargebinjie]

hello sixth,could you share your experience to us, don't just gave us a hope.

 

[dkumar]

Hello Sixth,

I am modeling the 5th order CT DS ADC in simulink and wanted to know how did you model the feedback DAC pulse? I have a 1bit switched Cap DAC and am trying to model with a linearly decaying triangular pulse which goes to zero at Ts/2. I am unable to figure out what should be the pulse height? or so to say, pulse area.
Would be nice if I can get some help from you.
Thanks much and looking for your response.
-Divya