Modeling asynchronous behavior in a NAND flash working in SDR mode.

[big_indian]

The figure above shows how an ONFI NAND flash memory is reset. Commands are latched onto the rising edge of WE_n. The Ready/Busy_n indicates an internal operation, and that the device is busy. Here, an internal reset is performed after receiving the command. It must be noted that there are no clock/reference signals while the internal reset is being performed, so reset is performed asynchronously and the device enters the Ready state after internal logic has been reset. IOx here can be thought of as IO[7:0], sometimes this is also called DQ[7:0]. DQS can be ignored, it is not specific to the SDR mode.

The figure above shows how block erase is done in a NAND flash. Here, we see that after receiving the appropriate commands and addresses, the corresponding block is erased asynchronously. R/B_n is tied to SR[6] (Status Register bit 6). Again, we see here that SR[6] goes low indicating the start of the block erase, and then goes high indicating the end of block erase, all of which happens asynchronously without any reference to any other signal in SDR mode. The other signals aren't displayed for the sake of simplicity, which is why I have displayed the command latch timings.
The issue here is the asynchronous rise of R/B_n and SR[6] after some operation is over. How can this be modeled? How do I begin to approach this?
The problem statement is: to model a circuit that captures the start of an event in a combinational circuit, and captures the end of a combinational event asynchronously. And if possible, to model this using verilog. ONFI protocol - https://onfi.org/files/onfi_4_2-gold.pdf

Thanks.

 

[FvM]

NAND flash controller is operating asynchronously in so far that the interface doesn't involve a clock signal, in contrast e.g. to DDR interface. This doesn't exclude usage of an internal clock for the controller state machine. Knowing that reset or erase operation runs over many us up to ms makes usage of an internal clock in the actual hardware very likely. A behavioral simulation model doesn't care for hardware implementation, it only relies on HDL timing statements.

So my first question is, are you trying to implement a simulation model or are you designing synthesizable hardware as a lab excercise?

I would describe the logic processing nWE input as edge triggered, even if it's comprised of gates at a low design level, similar to a master-slave FF.