sriramsv
Junior Member level 1
vsim-3036
Hi guys,
I'm getting this error in Modelsim when I try to simulate my codes:
# ** Error: (vsim-3036) Instantiation depth of '/ldpc_encoder2' is 81. Assuming recursive instantiation.
# Region: /ldpc_encoder2
# ** Error: (vsim-3036) Instantiation depth of '/ldpc_encoder2' is 82. Assuming recursive instantiation.
# Region: /ldpc_encoder2
# ** Error: (vsim-3036) Instantiation depth of '/ldpc_encoder2' is 83. Assuming recursive instantiation.
# Region: /ldpc_encoder2
# Error loading design
here is my code:
module Clock(clk);
output reg clk;
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
#500 $finish;
end
ldpc_encoder2 ld(mes, clk,s_out);
endmodule
module ldpc_encoder2(mes, clk,s_out);
input [15:0]mes;
input clk;
output [15:0]s_out;
//wire [15:0]s_in;
wire [15:0]q;
wire [15:0]p;
Clock c(clk);
D d_ff(.mes(mes),
.clk(clk),
.d_out(q));
SP sp(.s_in(q),
.clk(clk),
.s_out(p));
endmodule
module D(mes,clk,d_out);
input [15:0]mes;
input clk;
output reg [15:0]d_out;
wire [15:0]q;
assign q=d_out;
always @(posedge clk)
begin
d_out <= mes;
end
endmodule
module SP(s_in,clk,s_out);
input [15:0]s_in;
input clk;
output [15:0]s_out;
reg [15:0]p;
always @(posedge clk)
begin
p = {p[14:0],s_in};
end
assign s_out = p;
endmodule
Can anyone please suggest me what went wrong. I'm not able to fig it out.
Thanks
Sriram
Hi guys,
I'm getting this error in Modelsim when I try to simulate my codes:
# ** Error: (vsim-3036) Instantiation depth of '/ldpc_encoder2' is 81. Assuming recursive instantiation.
# Region: /ldpc_encoder2
# ** Error: (vsim-3036) Instantiation depth of '/ldpc_encoder2' is 82. Assuming recursive instantiation.
# Region: /ldpc_encoder2
# ** Error: (vsim-3036) Instantiation depth of '/ldpc_encoder2' is 83. Assuming recursive instantiation.
# Region: /ldpc_encoder2
# Error loading design
here is my code:
module Clock(clk);
output reg clk;
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
#500 $finish;
end
ldpc_encoder2 ld(mes, clk,s_out);
endmodule
module ldpc_encoder2(mes, clk,s_out);
input [15:0]mes;
input clk;
output [15:0]s_out;
//wire [15:0]s_in;
wire [15:0]q;
wire [15:0]p;
Clock c(clk);
D d_ff(.mes(mes),
.clk(clk),
.d_out(q));
SP sp(.s_in(q),
.clk(clk),
.s_out(p));
endmodule
module D(mes,clk,d_out);
input [15:0]mes;
input clk;
output reg [15:0]d_out;
wire [15:0]q;
assign q=d_out;
always @(posedge clk)
begin
d_out <= mes;
end
endmodule
module SP(s_in,clk,s_out);
input [15:0]s_in;
input clk;
output [15:0]s_out;
reg [15:0]p;
always @(posedge clk)
begin
p = {p[14:0],s_in};
end
assign s_out = p;
endmodule
Can anyone please suggest me what went wrong. I'm not able to fig it out.
Thanks
Sriram