[Mo]: How to make a design based on Nangate 15nm OCL in cadence virtuoso environment?

[william_luo]

Hi everyone,

I want to design a circuit under 15nm process technology, so I downloaded 15nm Nangate Open Cell Library (nangate.com) and corresponding PTM cards (ptm.asu.edu). But the 15nm Nangate OCL (2014_06.A) don't have virtuoso schematic cell (45nm or other Nangate OCL has the part).
Could anybody tell me how can I use the 15nm OCL file and model cards to make a design in virtuoso environment as I did in other process technology?

Thanks in advance!

Regards,
Wayne

 

[erikl]

Re: How to make a design based on Nangate 15nm OCL in cadence virtuoso environment?

I want to design a circuit under 15nm process technology, so I downloaded 15nm Nangate Open Cell Library (nangate.com) and corresponding PTM cards (ptm.asu.edu). But the 15nm Nangate OCL (2014_06.A) don't have virtuoso schematic cell (45nm or other Nangate OCL has the part).
Could anybody tell me how can I use the 15nm OCL file and model cards to make a design in virtuoso environment as I did in other process technology?

You could try and import the necessary schematics and symbols from the 45nm Nangate OCL lib and adapt them to the necessary parameters/pointers. Can't tell you exactly what you have to edit, but in former Cādence versions this worked via editing the cell's CDF: Tools/CDF/Edit -> Edit Component CDF .

 

[william_luo]

Thanks for your reply,
I actually copied the symbols of nmos4 and pmos4 from analogLib to a new library and edit the parameters of them by CDF. Then the spice netlists in 15nm OCL can be imported into cadence virtuoso environment based the new nmos4 and pmos4. I can use this new library to design and simulate.

Regards,