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mm-wave microstrip, cadence

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ivan848984

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Hello. I am designing a mm-wave LNA in CMOS 90 nm. I'm having difficulties in modeling microstrip lines, which i need instead of inductors. I have tried QRC RLC extraction and it extracts series R and L from a long straight line (metal 9, w = 5 um, l = 150 um -> L = 110 pH and R = 200 mOhms), which i pressume is ok. I have a few questions if someone can help me.

1) how accurate is QRC RLC extraction, for inductors value?
2) does cadence use microstrip (approximate) equations in RLC extraction. if so, where can i find dielectric thickess (is dielectric Si)? i have only found metal thickess in my PDKs.
Any other help and experience about this topic will be very helpful to me. Thanks.
 

I would expect 5% tolerance. Not that this answers your question in any way, but why are you going for a mm-wave on CMOS instead of SiGe? I assume SiGe wasn't available at 90nm or too expensive?
 
I have tried QRC RLC extraction and it extracts series R and L from a long straight line (metal 9, w = 5 um, l = 150 um -> L = 110 pH and R = 200 mOhms), which i pressume is ok.

The high frequency model for transmission lines consist of RLCG elements, as shown below. Extracting the line as RL only isn't accurate, unless the line is very short compared to wavelength. Only the RLCG model will give proper line impedance, delay and phase over a wide bandwidth.



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where can i find dielectric thickess (is dielectric Si)? i have only found metal thickess in my PDKs.

The PDKs usually include a cross section view, and thickness + material is documented in the cross section or in additional tables. The only parameter that isn't typically documented is bulk substrate conductivity.

You could also grab data from the Assura procfile, only the substrate itself isn't included there. I am using full wave EM solver for such analysis, and had created an EM stackup editor that can read/write many different file formats. You can use it to read and visualize the cross section if you have the Assura files.

https://muehlhaus.com/products/material-file-utility
 
I would expect 5% tolerance. Not that this answers your question in any way, but why are you going for a mm-wave on CMOS instead of SiGe? I assume SiGe wasn't available at 90nm or too expensive?

Yes, we currently only have CMOS 90nm tech.
 

Only the RLCG model will give proper line impedance, delay and phase over a wide bandwidth.
I'm not sure if it plays a role for for on-chip transmission lines, but a frequency independent RLCG model will only give correct results if the skin effect contribution to R is neglectible.
 

I'm not sure if it plays a role for for on-chip transmission lines, but a frequency independent RLCG model will only give correct results if the skin effect contribution to R is neglectible.

You are right. Strictly speaking, RLCG is extracted at a single frequency and the values are only exact at that frequency. What I tried to say is that transmission lines need a distributed L and C, and it's not enough to extract them as an inductance unless the line is short (electrical length < 0.1 wavelength or so).
 

What about custom inductors in Cadence? I have tried drawing a spiral square line (in metal 9) which would act as an inductor. I've run Quantus QRC RLCK extraction and measured Im{z11}/f to find inductance L and Im{z11}/Re{z11} to find Q. Inductance matches with theory (Bryan's formula). Also in Im{z11} series line parasitic inductors are dominative components, to circa 300 GHz which is a self-resonant frequency of the structure. So my question is, can an inductor be modeled like this (i would add later on some dummies, shields, guardrings), using layout+QRC? Thanks.
 

Always RLCK, never RLC.
Now a days PEEC is default, which is accurate.
For skin & proximity effect - use Ladder-network.
In usual GSG [Ground-Signal-Ground] please do include - ground strips in RLCK extraction, they have definite role..
If netlist size is too large - try RLCK reduction, however that costs additional license [which IMHO is reasonably good]
 
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